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| LXT9761/9781 Fast Ethernet 10/100 Multi-Port Transceiver with RMII Datasheet The LXT9781 is an eight-port PHY Fast Ethernet Transceiver that supports IEEE 802.3 physical layer applications at both 10 Mbps and 100 Mbps. It provides a Reduced Media Independent Interface (RMII) for switching and other independent port applications. The LXT9761 offers the same features and functionality in a six-port device. This data sheet uses the singular designation "LXT97x1" to refer to both devices. All network ports provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for a 10/100BASE-TX or 100BASE-FX connection. The LXT97x1 provides three discrete LED driver outputs for each port, as well as eight global serial LED outputs. The device supports both half- and full-duplex operation at 10 Mbps and 100 Mbps, and requires only a single 3.3V power supply. Applications s 100BASE-T, 10/100-TX, or 100BASE-FX Switches and multi-port NICs. Product Features s s s s s Six or eight IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports with integrated filters 3.3V operation Optimized for dual-high stacked R45 applications Proprietary Optimal Signal ProcessingTM architecture improves SNR by 3 dB over ideal analog filters Robust baseline wander correction 100BASE-FX fiber-optic capability on all ports s s s s s s s s Supports both auto-negotiation and legacy systems without auto-negotiation capability JTAG boundary scan Multiple Reduced MII (RMII) ports for independent PHY port operation Configurable via MDIO port or external control pins. Maskable interrupts Low power consumption (390 mW per port, typical) 208-pin PQFP (LXT9761 and LXT9781) 272-pin PBGA (LXT9781 only) As of January 15, 2001, this document replaces the Level One document LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII. Order Number: 249048-001 January 2001 Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT9761/9781 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Contents 1.0 2.0 Pin Assignments and Signal Descriptions....................................................10 Functional Description...........................................................................................21 2.1 Introduction..........................................................................................................21 2.1.1 OSPTM Architecture ................................................................................21 2.1.2 Comprehensive Functionality .................................................................21 Interface Descriptions..........................................................................................22 2.2.1 10/100 Network Interface .......................................................................22 2.2.1.1 Twisted-Pair Interface ...............................................................22 2.2.1.2 Fiber Interface ...........................................................................23 2.2.2 RMII Interface.........................................................................................23 2.2.3 Configuration Management Interface .....................................................23 2.2.3.1 MDIO Management Interface ....................................................23 2.2.3.2 Hardware Control Interface .......................................................25 Operating Requirements .....................................................................................25 2.3.1 Power Requirements..............................................................................25 2.3.2 Clock Requirements ...............................................................................26 2.3.2.1 Reference Clock ........................................................................26 Initialization..........................................................................................................26 2.4.1 MDIO Control Mode ...............................................................................26 2.4.2 Hardware Control Mode .........................................................................26 2.4.3 Power-Down Mode.................................................................................27 2.4.3.1 Global (Hardware) Power Down................................................27 2.4.3.2 Port (Software) Power Down .....................................................27 2.4.4 Reset ......................................................................................................28 2.4.5 Hardware Configuration Settings ...........................................................28 Link Establishment ..............................................................................................29 2.5.1 Auto-Negotiation.....................................................................................29 2.5.1.1 Base Page Exchange................................................................29 2.5.1.2 Next Page Exchange.................................................................29 2.5.1.3 Controlling Auto-Negotiation .....................................................29 2.5.2 Parallel Detection ...................................................................................30 RMII Operation ....................................................................................................30 2.6.1 Reference Clock.....................................................................................31 2.6.2 Transmit Enable .....................................................................................31 2.6.3 Carrier Sense & Data Valid ....................................................................31 2.6.4 Receive Error .........................................................................................31 2.6.5 Loopback................................................................................................31 2.6.6 Out of Band Signalling............................................................................31 2.6.7 4B/5B Coding Operations.......................................................................32 100 Mbps Operation............................................................................................32 2.7.1 100BASE-X Network Operations ...........................................................32 2.7.2 100BASE-X Protocol Sublayer Operations ............................................33 2.7.2.1 PCS Sublayer ............................................................................33 2.7.2.2 PMA Sublayer ...........................................................................35 2.7.2.3 Twisted-Pair PMD Sublayer ......................................................36 2.7.2.4 Fiber PMD Sublayer ..................................................................37 2.2 2.3 2.4 2.5 2.6 2.7 Datasheet 3 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII 2.8 2.9 2.10 10 Mbps Operation.............................................................................................. 37 2.8.1 Preamble Handling................................................................................. 37 2.8.2 Dribble Bits............................................................................................. 38 2.8.3 Link Test................................................................................................. 38 2.8.3.1 Link Failure................................................................................ 38 2.8.4 Jabber .................................................................................................... 38 Monitoring Operations......................................................................................... 38 2.9.1 Monitoring Auto-Negotiation................................................................... 38 2.9.2 Serial LED Functions ............................................................................. 38 2.9.3 Per-Port LED Driver Functions............................................................... 40 2.9.3.1 LED Pulse Stretching ................................................................ 40 2.9.4 Using the Quick Status Register ............................................................ 41 2.9.5 Out-of-Band Signalling ........................................................................... 42 Boundary Scan (JTAG1149.1) Functions ........................................................... 42 2.10.1 Boundary Scan Interface........................................................................ 42 2.10.2 State Machine ........................................................................................ 42 2.10.3 Instruction Register ................................................................................ 43 2.10.4 Boundary Scan Register ........................................................................ 43 Design Recommendations .................................................................................. 44 3.1.1 General Design Guidelines .................................................................... 44 3.1.2 Power Supply Filtering ........................................................................... 44 3.1.3 Power and Ground Plane Layout Considerations .................................. 45 3.1.3.1 Chassis Ground......................................................................... 45 3.1.4 RMII Terminations .................................................................................. 45 3.1.5 The RBIAS Pin ....................................................................................... 45 3.1.6 The Twisted-Pair Interface ..................................................................... 46 3.1.6.1 Magnetics Information ............................................................... 46 3.1.7 The Fiber Interface................................................................................. 46 Typical Application Circuits ................................................................................. 46 3.0 Application Information......................................................................................... 44 3.1 3.2 4.0 5.0 6.0 Test Specifications.................................................................................................. 52 Register Definitions ................................................................................................ 62 Package Specifications ......................................................................................... 77 4 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 LXT9781 Block Diagram ....................................................................................... 9 LXT9781 PQFP Pin Assignments .......................................................................10 LXT9781 PBGA Pin Assignments ......................................................................11 LXT9761 PQFP Pin Assignments .......................................................................12 LXT97x1 Interfaces ............................................................................................22 Port Address Scheme .........................................................................................24 Management Interface Read Frame Structure ...................................................24 Management Interface Write Frame Structure ...................................................24 Interrupt Logic .....................................................................................................25 Initialization Sequence .......................................................................................27 Hardware Control Settings .................................................................................28 Auto-Negotiation Operation ................................................................................30 Loopback Paths ..................................................................................................31 RMII Data Flow ...................................................................................................32 100BASE-X Frame Format ................................................................................33 Protocol Sublayers .............................................................................................34 Serial LED Streams.............................................................................................39 LED Pulse Stretching ..........................................................................................41 Quick Status Register..........................................................................................41 RMII Programmable Out of Band Signalling .......................................................42 Power and Ground Supply Connections ............................................................47 Typical Twisted-Pair Interface ............................................................................48 Typical Fiber Interface ........................................................................................49 Typical RMII Interface ........................................................................................50 Typical Serial LED Interface................................................................................51 100BASE-TX Receive Timing ...........................................................................55 100BASE-TX Transmit Timing ..........................................................................55 100BASE-FX Receive Timing ...........................................................................56 100BASE-FX Transmit Timing ..........................................................................57 10BASE-T Receive Timing ................................................................................57 10BASE-T Transmit Timing ...............................................................................58 Auto-Negotiation and Fast Link Pulse Timing ...................................................59 Fast Link Pulse Timing .......................................................................................59 MDIO Write Timing (MDIO Sourced by MAC) ....................................................60 MDIO Read Timing (MDIO Sourced by PHY) ....................................................60 Power-Up Timing ................................................................................................61 RESET And Power-Down Recovery Timing ......................................................61 PHY Identifier Bit Mapping .................................................................................67 LXT97x1 PQFP Specification .............................................................................77 LXT9781 PBGA Specification .............................................................................78 Tables 1 2 3 4 5 LXT97x1 RMII Signal Descriptions......................................................................13 LXT97x1 Signal Detect/TP Select Signal Descriptions .......................................15 LXT97x1 Network Interface Signal Descriptions .................................................16 LXT97x1 JTAG Test Signal Descriptions ............................................................16 LXT97x1 Miscellaneous Signal Descriptions ......................................................17 Datasheet 5 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 LXT97x1 Power Supply Signal Descriptions....................................................... 18 LXT97x1 LED Signal Descriptions ...................................................................... 19 Unused Pins........................................................................................................ 20 Hardware Configuration Settings ........................................................................ 29 4B/5B Coding ...................................................................................................... 34 BSR Mode of Operation ...................................................................................... 43 Supported JTAG Instructions .............................................................................. 43 Device ID Register .............................................................................................. 43 Magnetics Requirements .................................................................................... 46 Absolute Maximum Ratings ................................................................................ 52 Operating Conditions .......................................................................................... 52 Digital I/O Characteristics 1................................................................................. 52 Digital I/O Characteristics - RMII Pins ................................................................. 53 Required Clock Characteristics........................................................................... 53 100BASE-TX Transceiver Characteristics .......................................................... 53 100BASE-FX Transceiver Characteristics .......................................................... 54 10BASE-T Transceiver Characteristics............................................................... 54 100BASE-TX Receive Timing Parameters ......................................................... 55 100BASE-TX Transmit Timing Parameters ........................................................ 56 100BASE-FX Receive Timing Parameters ......................................................... 56 100BASE-FX Transmit Timing Parameters ........................................................ 57 10BASE-T Receive Timing Parameters.............................................................. 58 10BASE-T Transmit Timing Parameters............................................................. 58 Auto-Negotiation and Fast Link Pulse Timing Parameters ................................. 59 MDIO Timing Parameters ................................................................................... 60 Power-Up Timing Parameters............................................................................ 61 RESET and Power-Down Recovery Timing Parameters ................................... 61 Register Set ........................................................................................................ 62 Register Bit Map.................................................................................................. 63 Control Register (Address 0)............................................................................... 65 Status Register (Address 1) ................................................................................ 65 PHY Identification Register 1 (Address 2)........................................................... 66 PHY Identification Register 2 (Address 3)........................................................... 67 Auto-Negotiation Advertisement Register (Address 4) ....................................... 67 Auto-Negotiation Link Partner Base Page Ability Register (Address 5) .............. 68 Auto-Negotiation Expansion (Address 6) ............................................................ 69 Auto-Negotiation Next Page Transmit Register (Address 7)............................... 69 Auto-Negotiation Link Partner Next Page Receive Register (Address 8) ........... 70 Port Configuration Register (Address 16, Hex 10) .............................................. 70 Quick Status Register (Address 17, Hex 11) ...................................................... 71 Interrupt Enable Register (Address 18, Hex 12) ................................................. 72 Interrupt Status Register (Address 19, Hex 13) .................................................. 73 LED Configuration Register (Address 20, Hex 14) ............................................. 74 Out of Band Signaling Register (Address 25) ..................................................... 75 Transmit Control Register #1 (Address 28)......................................................... 76 Transmit Control Register #2 (Address 30)......................................................... 76 6 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Revision History Revision Date Description Datasheet 7 Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Figure 1. LXT9781 Block Diagram REFCLK QSTAT QCLK ADD<4:0> MDIO MDC MDINT Management / Mode Select Logic Global Functions Clock Generator Pwr Supply / PwrDown VCC GND PWRDWN RESET 8 Register Set TX PCS TXENn RMII TXDn_0 TXDn_1 Manchester 10 Encoder Parallel/Serial Converter Scrambler 100 & Encoder Auto Negotiation TP Driver + + TP / Fiber Out LEDS<7:0> LEDLATCH LEDCLK OSP TM Pulse Shaper TPFOPn TPFONn Mgmt Counters Register Set CIM ECL Driver SDn/TXn OSP TM Clock Generator Media Select Adaptive EQ with BaseLine Wander Cancellation 100TX + + 100FX RMII RX PCS RXDn_0 RXDn_1 CRS_DVn RXERn Carrier Sense Data Valid Error Detect Serial to Parallel Converter 10 100 Manchester Decoder Decoder & Descrambler OSP TM Slicer TP / Fiber In TPFIPn TPFINn + 10BT PORT 0 Per-Port Functions - PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 Datasheet 9 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII 1.0 Pin Assignments and Signal Descriptions Figure 2. LXT9781 PQFP Pin Assignments 208 ..........VCCIO 207 ..........QCLK 206 ..........QSTAT 205 ..........LED/CFG0_3 204 ..........LED/CFG0_2 203 ..........LED/CFG0_1 202 ..........LED/CFG1_3 201 ..........LED/CFG1_2 200 ..........LED/CFG1_1 199 ..........LED/CFG2_3 198 ..........LED/CFG2_2 197 ..........LED/CFG2_1 196 ..........LED/CFG3_3 195 ..........LED/CFG3_2 194 ..........LED/CFG3_1 193 ..........VCCIO 192 ..........GNDD 191 ..........LED/CFG4_3 190 ..........LED/CFG4_2 189 ..........LED/CFG4_1 188 ..........LED/CFG5_3 187 ..........LED/CFG5_2 186 ..........LED/CFG5_1 185 ..........LED/CFG6_3 184 ..........LED/CFG6_2 183 ..........LED/CFG6_1 182 ..........LED/CFG7_3 181 ..........LED/CFG7_2 180 ..........LED/CFG7_1 179 ..........VCCD 178 ..........GNDD 177 ..........LEDS0 176 ..........LEDS1 175 ..........LEDS2 174 ..........LEDS3 173 ..........LEDS4 172 ..........LEDS5 171 ..........LEDS6 170 ..........LEDS7 169 ..........LEDLATCH 168 ..........LEDCLK 167 .......... TRST 166 ..........TCK 165 ..........TMS 164 ..........TDO 163 ..........TDI 162 ..........SD/TP4 161 ..........SD/TP5 160 ..........SD/TP6 159 ..........SD/TP7 158 ..........GNDA 157 ..........TPFIP7 1. Ports 6 and 7 are available only on the LXT9781. These ports are not bonded out on the LXT9761. Package Topside Markings Marking Part # Rev # Lot # FPO # Definition LXT9781 is the unique identifier for this product family. Identifies the particular silicon "stepping" (Refer to Specification Update for additional stepping information.) Identifies the batch. Identifies the Finish Process Order. 10 GNDD ...... 53 RXD1_1 ...... 54 RXD1_0 ...... 55 CRS_DV1 ...... 56 RXER1 ...... 57 TXEN1 ...... 58 TXD1_0 ...... 59 TXD1_1 ...... 60 RXD0_1 ...... 61 RXD0_0 ...... 62 CRS_DV0 ...... 63 RXER0 ...... 64 TXEN0 ...... 65 TXD0_0 ...... 66 VCCIO ...... 67 GNDD ...... 68 TXD0_1 ...... 69 MDC ...... 70 MDIO ...... 71 GNDD ...... 72 GNDD ...... 73 GNDD ...... 74 GNDD ...... 75 TxSLEW_0 ...... 76 TxSLEW_1 ...... 77 GNDS ...... 78 PAUSE ...... 79 VCCD ...... 80 GNDD ...... 81 PWRDWN ...... 82 RESET ...... 83 MDINT ...... 84 MDDIS ...... 85 GNDD ...... 86 GNDD ...... 87 VCCD ...... 88 GNDD ...... 89 GNDD ...... 90 GNDD ...... 91 REFCLK ...... 92 ADD_0 ...... 93 ADD_1 ...... 94 ADD_2 ...... 95 ADD_3 ...... 96 ADD_4 ...... 97 SD/TP3 ...... 98 SD/TP2 ...... 99 SD/TP1 ...... 100 SD/TP0 ...... 101 RBIAS ...... 102 GNDA ...... 103 TPFIP0 ...... 104 GNDD .......1 RXD7_1 .......2 RXD7_0 .......3 CRS_DV7 .......4 RXER7 .......5 TXEN7 .......6 TXD7_0 .......7 TXD7_1 .......8 RXD6_1 .......9 RXD6_0 .......10 CRS_DV6 .......11 RXER6 .......12 TXEN6 .......13 TXD6_0 .......14 VCCIO .......15 GNDD .......16 TXD6_1 .......17 RXD5_1 .......18 RXD5_0 .......19 CRS_DV5 .......20 RXER5...... 21 TXEN5 .......22 TXD5_0 .......23 TXD5_1 .......24 RXD4_1 .......25 RXD4_0 .......26 CRS_DV4 .......27 RXER4 .......28 TXEN4 .......29 TXD4_0 .......30 VCCIO .......31 GNDD .......32 TXD4_1 .......33 RXD3_1 .......34 RXD3_0 .......35 CRS_DV3 .......36 RXER3 .......37 TXEN3 .......38 TXD3_0 .......39 TXD3_1 .......40 RXD2_1 .......41 RXD2_0 .......42 CRS_DV2 .......43 RXER2 .......44 TXEN2 .......45 TXD2_0 .......46 TXD2_1 .......47 GNDD .......48 GNDD .......49 GNDD .......50 GNDD .......51 VCCIO .......52 Part # LOT # FPO # LXT9781 XX XXXXXX XXXXXXXX Rev # 156 ..........TPFIN7 155 ..........VCCR 154 ..........TPFOP7 153 ..........TPFON7 152 ..........GNDA 151 ..........TPFON6 150 ..........TPFOP6 149 ..........VCCT 148 ..........VCCR 147 ..........TPFIN6 146 ..........TPFIP6 145 ..........GNDA 144 ..........GNDA 143 ..........TPFIP5 142 ..........TPFIN5 141 ..........VCCR 140 ..........TPFOP5 139 ..........TPFON5 138 ..........GNDA 137 ..........TPFON4 136 ..........TPFOP4 135 ..........VCCT 134 ..........VCCR 133 ..........TPFIN4 132 ..........TPFIP4 131 ..........GNDA 130 ..........GNDA 129 ..........TPFIP3 128 ..........TPFIN3 127 ..........VCCR 126 ..........VCCT 125 ..........TPFOP3 124 ..........TPFON3 123 ..........GNDA 122 ..........TPFON2 121 ..........TPFOP2 120 ..........VCCR 119 ..........TPFIN2 118 ..........TPFIP2 117 ..........GNDA 116 ..........GNDA 115 ..........TPFIP1 114 ..........TPFIN1 113 ..........VCCR 112 ..........VCCT 111 ..........TPFOP1 110 ..........TPFON1 109 ..........GNDA 108 ..........TPFON0 107 ..........TPFOP0 106 ..........VCCR 105 ..........TPFIN0 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Figure 3. LXT9781 PBGA Pin Assignments 1 A B C D E F G H J K L M N P R T U V W Y N/C 2 N/C 3 QCLK 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TRST SD6/ TP6 SD5/ TP5 SD7/ TP7 VCCT TP FIN7 TP FON7 TP FOP6 TP FIP6 TP FIP7 TP FOP7 TP FON6 TP FIN6 LED/ LED/ LED/ LED/ LED/ LED/ LED/ GNDD CFG1_2 CFG2_2 CFG3_1 CFG4_2 CFG5_2 CFG6_1 CFG7_3 VCCD LEDS_4 LEDS_3 LEDS_7 LED/ LED/ VCCD CFG5_3 CFG6_2 LED CLK A B C D E F G H J K L M N P R T U V W Y N/C LED/ LED/ GNDD CRS_DV7 QSTAT CFG0_1 LED/ CFG2_3 CFG3_3 RXD7 _0 GNDD VCCD LEDS_1 LEDS_5 TMS VCCT RXD7 _1 GNDD LED/ LED/ LED/ LED/ LED/ GNDD LEDS_2 LEDS_6 VCCIO CFG0_3 LED/ CFG2_1 CFG4_1 CFG6_3 LED/ CFG1_3 CFG7_2 CFG7_1 TXD7 _1 LED/ LED/ LED/ LED/ LED/ GNDD CFG0_2 CFG1_1 CFG3_2 CFG4_3 CFG5_1 LEDS _0 LED LATCH TDO SD4/ TP4 GNDA RXER7 TXEN7 TXD7 _0 RXD6 _0 VCCIO TDI TCK GNDA VCCR GNDA RXD6 _1 GNDD GNDD VCCR GNDA VCCT VCCT CRS_DV6 RXER6 TXEN6 TXD6 _0 VCCIO TXD6 _1 GNDD GNDD TOP VIEW LXT9781BC GNDD GNDD GNDD GNDD GNDA GNDA TP FIN5 TP FON5 TP FOP4 TP FIN4 TP FIP5 TP FOP5 TP FON4 TP FIP4 GNDA GNDA RXD5 _1 GNDD RXD5 _0 TXD5 _0 RXD4 _0 TXD4 _0 CRS_ DV5 TXD5 _1 CRS_ DV4 VCCR GNDA RXER5 TXEN5 VCCR GNDA GNDD RXD4 _1 GNDD GNDD GNDD GNDD GNDA GNDA VCCT VCCT RXER4 TXEN4 TXD4_1 GNDD GNDD GNDD GNDD GNDA GNDA VCCT VCCT VCCIO GNDD GNDD GNDD GNDD GNDD GNDD GNDD VCCR GNDA TP FIN3 TP FON3 TP FOP2 TP FIP2 TP FIP3 TP FOP3 TP FON2 TP FIN2 RXD3 _1 RXD3 _0 CRS_ DV3 TXD3 _0 CRS_ DV2 TXD2 _1 RXER3 VCCR GNDA TXEN3 GNDD TXD3 _1 GNDA GNDA RXD2 _1 RXD2 _0 TXD2 _0 RXER2 GNDA GNDA TXEN2 GNDD VCCR GNDA VCCT VCCT N/C N/C N/C N/C GNDD RXD0 _1 CRS_ DV0 RXD0 _0 TXD0 _0 GNDD N/C TxSLEW_1 GNDD MDINT SD1/ TP1 SD2/ TP2 SD3/ TP3 GNDA VCCR GNDA TP FIN1 TP FON1 TP FOP0 TP FIP0 TP FIP1 TP FOP1 TP FON0 TP FIN0 VCCIO RXD1 _1 RXER1 TXD1 _1 TXD1 _0 GNDD MDC N/C GNDS GNDD RESET ADD_2 ADD_1 ADD_3 SD0/ TP0 RBIAS GNDA N/C GNDD TXEN1 GNDD RXER0 TXD0_1 MDIO N/C PAUSE GNDD PWRDWN GNDD GNDD ADD_0 ADD_4 GNDA VCCT N/C RXD1 _0 CRS_ DV1 N/C TXEN0 VCCIO N/C TxSLEW_0 VCCD VCCD VCCD MDDIS GNDD GNDD REFCLK GNDD GNDD VCCT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1. Ports 6 and 7 are available only on the LXT9781. Datasheet 11 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Figure 4. LXT9761 PQFP Pin Assignments 208 ..........VCCIO 207 ..........QCLK 206 ..........QSTAT 205 ..........LED/CFG0_3 204 ..........LED/CFG0_2 203 ..........LED/CFG0_1 202 ..........LED/CFG1_3 201 ..........LED/CFG1_2 200 ..........LED/CFG1_1 199 ..........LED/CFG2_3 198 ..........LED/CFG2_2 197 ..........LED/CFG2_1 196 ..........N/C 195 ..........N/C 194 ..........N/C 193 ..........VCCIO 192 ..........GNDD 191 ..........N/C 190 ..........N/C 189 ..........N/C 188 ..........LED/CFG3_3 187 ..........LED/CFG3_2 186 ..........LED/CFG3_1 185 ..........LED/CFG4_3 184 ..........LED/CFG4_2 183 ..........LED/CFG4_1 182 ..........LED/CFG5_3 181 ..........LED/CFG5_2 180 ..........LED/CFG5_1 179 ..........VCCD 178 ..........GNDD 177 ..........LEDS0 176 ..........LEDS1 175 ..........LEDS2 174 ..........LEDS3 173 ..........LEDS4 172 ..........LEDS5 171 ..........LEDS6 170 ..........LEDS7 169 ..........LEDLATCH 168 ..........LEDCLK 167 .......... TRST 166 ..........TCK 165 ..........TMS 164 ..........TDO 163 ..........TDI 162 ..........N/C 161 ..........SD/TP3 160 ..........SD/TP4 159 ..........SD/TP5 158 ..........GNDA 157 ..........TPFIP5 GNDD ...... 1 RXD5_1 ...... 2 RXD5_0 ...... 3 CRS_DV5 ...... 4 RXER5 ...... 5 TXEN5 ...... 6 TXD5_0 ...... 7 TXD5_1 ...... 8 RXD4_1 ...... 9 RXD4_0 ...... 10 CRS_DV4 ...... 11 RXER4 ...... 12 TXEN4 ...... 13 TXD4_0 ...... 14 VCCIO ...... 15 GNDD ...... 16 TXD4_1 ...... 17 RXD3_1 ...... 18 RXD3_0 ...... 19 CRS_DV3 ...... 20 RXER3 ...... 21 TXEN3 ...... 22 TXD3_0 ...... 23 TXD3_1 ...... 24 N/C ...... 25 N/C ...... 26 N/C ...... 27 N/C ...... 28 N/C ...... 29 N/C ...... 30 VCCIO ...... 31 GNDD ...... 32 N/C ...... 33 N/C ...... 34 N/C ...... 35 N/C ...... 36 N/C ...... 37 N/C ...... 38 N/C ...... 39 N/C ...... 40 RXD2_1 ...... 41 RXD2_0 ...... 42 CRS_DV2 ...... 43 RXER2 ...... 44 TXEN2 ...... 45 TXD2_0 ...... 46 TXD2_1 ...... 47 GNDD ...... 48 GNDD ...... 49 GNDD ...... 50 GNDD ...... 51 VCCIO ...... 52 Part # LOT # FPO # LXT9761 XX XXXXXX XXXXXXXX Rev 156 ..........TPFIN5 155 ..........VCCR 154 ..........TPFOP5 153 ..........TPFON5 152 ..........GNDA 151 ..........TPFON4 150 ..........TPFOP4 149 ..........VCCT 148 ..........VCCR 147 ..........TPFIN4 146 ..........TPFIP4 145 ..........GNDA 144 ..........GNDA 143 ..........TPFIP3 142 ..........TPFIN3 141 ..........VCCR 140 ..........TPFOP3 139 ..........TPFON3 138 ..........GNDA 137 ..........N/C 136 ..........N/C 135 ..........N/C 134 ..........N/C 133 ..........N/C 132 ..........N/C 131 ..........N/C 130 ..........N/C 129 ..........N/C 128 ..........N/C 127 ..........N/C 126 ..........N/C 125 ..........N/C 124 ..........N/C 123 ..........GNDA 122 ..........TPFON2 121 ..........TPFOP2 120 ..........VCCR 119 ..........TPFIN2 118 ..........TPFIP2 117 ..........GNDA 116 ..........GNDA 115 ..........TPFIP1 114 ..........TPFIN1 113 ..........VCCR 112 ..........VCCT 111 ..........TPFOP1 110 ..........TPFON1 109 ..........GNDA 108 ..........TPFON0 107 ..........TPFOP0 106 ..........VCCR 105 ..........TPFIN0 1. Ports 6 and 7 are available only on the LXT9781. Package Topside Markings Marking Part # Rev # Lot # FPO # Definition LXT9761 is the unique identifier for this product family. Identifies the particular silicon "stepping" (Refer to Specification Update for additional stepping information.) Identifies the batch. Identifies the Finish Process Order. 12 GNDD .......53 RXD1_1 .......54 RXD1_0 .......55 CRS_DV1 .......56 RXER1 .......57 TXEN1 .......58 TXD1_0 .......59 TXD1_1 .......60 RXD0_1 .......61 RXD0_0 .......62 CRS_DV0 .......63 RXER0 .......64 TXEN0 .......65 TXD0_0 .......66 VCCIO .......67 GNDD .......68 TXD0_1 .......69 MDC .......70 MDIO .......71 GNDD .......72 GNDD .......73 GNDD .......74 GNDD .......75 TxSLEW_0 .......76 TxSLEW_1 .......77 GNDS .......78 PAUSE .......79 VCCD .......80 GNDD .......81 PWRDWN .......82 RESET .......83 MDINT .......84 MDDIS .......85 VCCD .......86 GNDD .......87 VCCD .......88 GNDD .......89 GNDD .......90 GNDD .......91 REFCLK .......92 ADD_0 .......93 ADD_1 .......94 ADD_2 .......95 ADD_3 .......96 ADD_4 .......97 N/C .......98 SD/TP2 .......99 SD/TP1 .......100 SD/TP0 .......101 RBIAS .......102 GNDA .......103 TPFIP0 .......104 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Table 1. 9761 Pin# PQFP LXT97x1 RMII Signal Descriptions 9781 Pin# Symbol PQFP PBGA RMII Data Interface Pins Reference Clock. 50 MHz RMII reference clock is required at this pin. The LXT97x1 samples RMII inputs on the rising edge of REFCLK, and drives RMII outputs on the falling edge. Transmit Data - Port 0. Inputs containing 2-bit parallel di-bits to be transmitted from port 0 are clocked in synchronously to REFCLK. Transmit Data - Port 1. Inputs containing 2-bit parallel di-bits to be transmitted from port 1 are clocked in synchronously to REFCLK. Transmit Data - Port 2. Inputs containing 2-bit parallel di-bits to be transmitted from port 2 are clocked in synchronously to REFCLK. Transmit Data - Port 3. Inputs containing 2-bit parallel di-bits to be transmitted from port 3 are clocked in synchronously to REFCLK. Transmit Data - Port 4. Inputs containing 2-bit parallel di-bits to be transmitted from port 4 are clocked in synchronously to REFCLK. Transmit Data - Port 5. Inputs containing 2-bit parallel di-bits to be transmitted from port 5 are clocked in synchronously to REFCLK. Transmit Data - Port 6. Inputs containing 2-bit parallel di-bits to be transmitted from port 6 are clocked in synchronously to REFCLK. Transmit Data - Port 7. Inputs containing 2-bit parallel di-bits to be transmitted from port 7 are clocked in synchronously to REFCLK. Type1 Signal Description2, 3 92 92 Y15 REFCLK I 66 69 59 60 46 47 23 24 14 17 7 8 66 69 59 60 46 47 39 40 30 33 23 24 14 17 7 8 V7 W7 W4 V4 T2 T3 P3 P4 L3 L4 J3 J4 F4 G2 D3 D4 Y5 TXD0_0 TXD0_1 TXD1_0 TXD1_1 TXD2_0 TXD2_1 TXD3_0 TXD3_1 TXD4_0 TXD4_1 TXD5_0 TXD5_1 TXD6_0 TXD6_1 TXD7_0 TXD7_1 I I I I I I - I - I 65 58 45 22 13 6 - - 62 61 55 54 65 58 45 38 29 22 13 6 62 61 55 54 W3 T1 P1 L2 J2 F3 D2 U7 U6 Y2 V2 TXEN0 TXEN1 TXEN2 TXEN3 TXEN4 TXEN5 TXEN6 TXEN7 RXD0_0 RXD0_1 RXD1_0 RXD1_1 I Transmit Enable - Ports 0 - 7. Active High input enables respective port transmitter. This signal must be synchronous to the REFCLK. O O Receive Data - Port 0. Receive data signals (2-bit parallel dibits) are driven synchronously to REFCLK. Receive Data - Port 1. Receive data signals (2-bit parallel dibits) are driven synchronously to REFCLK. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain 2. The LXT97x1 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). 3. Ports 6 and 7 are available only on the LXT9781. These pins are not bonded out on the LXT9761. Datasheet 13 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 1. 9761 Pin# PQFP 42 41 19 18 10 9 3 2 - - - - 63 56 43 20 11 4 - - LXT97x1 RMII Signal Descriptions (Continued) 9781 Pin# Symbol PQFP 42 41 35 34 26 25 19 18 10 9 3 2 63 56 43 36 27 20 11 4 PBGA R2 R1 N2 N1 K3 K2 H3 H1 E3 E1 C2 C1 V6 Y3 R3 N3 K4 H4 F1 B3 W6 CRS_DV0 CRS_DV1 CRS_DV2 CRS_DV3 CRS_DV4 CRS_DV5 CRS_DV6 CRS_DV7 RXD2_0 RXD2_1 RXD3_0 RXD3_1 RXD4_0 RXD4_1 RXD5_0 RXD5_1 RXD6_0 RXD6_1 RXD7_0 RXD7_1 O O O O O O Receive Data - Port 2. Receive data signals (2-bit parallel dibits) are driven synchronously to REFCLK. Receive Data - Port 3. Receive data signals (2-bit parallel dibits) are driven synchronously to REFCLK. Receive Data - Port 4. Receive data signals (2-bit parallel dibits) are driven synchronously to REFCLK. Receive Data - Port 5. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Receive Data - Port 6. Receive data signals (2-bit parallel dibits) are driven synchronously to REFCLK. Receive Data - Port 7. Receive data signals (2-bit parallel di-bits) are driven synchronously to REFCLK. Type1 Signal Description2, 3 O Carrier Sense/Receive Data Valid - Ports 0 - 7. On detection of valid carrier, these signals are asserted asynchronously with respect to REFCLK. CRS_DVn is deasserted on loss of carrier, synchronous to REFCLK. 64 57 44 21 12 5 - - 64 57 44 37 28 21 12 5 V3 R4 N4 L1 J1 F2 D1 RXER0 RXER1 RXER2 RXER3 RXER4 RXER5 RXER6 RXER7 O Receive Error - Ports 0 - 7. These signals are synchronous to the respective REFCLK. Active High indicates that received code group is invalid, or that PLL is not locked. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain 2. The LXT97x1 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). 3. Ports 6 and 7 are available only on the LXT9781. These pins are not bonded out on the LXT9761. 14 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Table 1. 9761 Pin# PQFP LXT97x1 RMII Signal Descriptions (Continued) 9781 Pin# Symbol PQFP PBGA RMII Control Interface Pins Type1 Signal Description2, 3 70 70 V8 MDC I Management Data Clock. Clock for the MDIO serial data channel. Maximum frequency is 8 MHz. Management Data Input/Output. Bidirectional serial data channel for PHY/STA communication. Management Data Interrupt. When bit 18.1 = 1, an active Low output on this pin indicates status change. Interrupt is cleared when Register 19 is read. Management Disable. When MDDIS is High, the MDIO is disabled from read and write operations. When MDDIS is Low at power up or reset, the Hardware Control Interface pins control only the initial or "default" values of their respective register bits. After the power-up/ reset cycle is complete, bit control reverts to the MDIO serial channel. 71 71 W8 MDIO I/O 84 84 U12 MDINT OD 85 85 Y12 MDDIS I 1. Type Column Coding: I = Input, O = Output, OD = Open Drain 2. The LXT97x1 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). 3. Ports 6 and 7 are available only on the LXT9781. These pins are not bonded out on the LXT9761. Table 2. 9761 Pin# PQFP 101 100 99 161 160 159 - - LXT97x1 Signal Detect/TP Select Signal Descriptions 9781 Pin# Symbol PQFP 101 100 99 98 162 161 160 159 PBGA V16 U13 U14 U15 C16 B17 A17 C17 SD0/TP0 SD1/TP1 SD2/TP2 SD3/TP3 SD4/TP4 SD5/TP5 SD6/TP6 SD7/TP7 I Signal Detect - Ports 0 - 7. Tying the SD/TPn pins High or to a PECL input sets bit 16.0 = 1 and the respective port is forced to FX mode. In the absence of an active link, the pin must be pulled High to enable loopback in FX mode. Do not enable Auto-Negotiation if FX mode is selected. The SD/TPn pins have internal pull-downs. When not using FX mode, SD/TPn pins should be tied to GNDA. TP Select - Ports 0 - 7. Tying the SD/TPn pins Low sets bit 16.0 = 0 and forces the respective port to TP mode. Type1 Signal Description2 1. Type Column Coding: I = Input, O = Output. 2. Ports 6 and 7 are available only on the LXT9781. These pins are not bonded out on the LXT9761. Datasheet 15 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 3. 9761 Pin# PQFP LXT97x1 Network Interface Signal Descriptions 9781 Pin# PQFP PBGA W19, W20 Twisted-Pair/Fiber Outputs, Positive & Negative - Ports 0-7. AO During 100BASE-TX or 10BASE-T operation, TPFO pins drive 802.3 compliant pulses onto the line. During 100BASE-FX operation, TPFO pins produce differential PECL outputs for fiber transceivers. Symbol Type1 Signal Description2 107, 108 111, 110 121, 122 140, 139 150, 151 154, 153 -, - -, - 107, 108 111, 110 121, 122 125, 124 136, 137 140, 139 150, 151 154, 153 V20, V19 P19, P20 N20, N19 H19, H20 G20, G19 C19, C20 B20, B19 Y19, Y20 TPFOP0, TPFON0 TPFOP1, TPFON1 TPFOP2, TPFON2 TPFOP3, TPFON3 TPFOP4, TPFON4 TPFOP5, TPFON5 TPFOP6, TPFON6 TPFOP7, TPFON7 104, 105 115, 114 118, 119 143, 142 146, 147 157, 156 -, - -, - 104, 105 115, 114 118, 119 129, 128 132, 133 143, 142 146, 147 157, 156 U20, U19 R19, R20 M20, M19 J20, J19 F20, F19 D19, D20 A20, A19 TPFIP0, TPFIN0 TPFIP1, TPFIN1 TPFIP2, TPFIN2 TPFIP3, TPFIN3 TPFIP4, TPFIN4 TPFIP5, TPFIN5 TPFIP6, TPFIN6 TPFIP7, TPFIN7 Twisted-Pair/Fiber Inputs, Positive & Negative - Ports 0-7. AI During 100BASE-TX or 10BASE-T operation, TPFI pins receive differential 100BASE-TX or 10BASE-T signals from the line. During 100BASE-FX operation, TPFI pins receive differential PECL inputs from fiber transceivers. 1. Type Column Coding: I = Input, O = Output. 2. Ports 6 and 7 are available only on the LXT9781. These pins are not bonded out on the LXT9761. Table 4. PQFP Pin#1 163 164 165 166 167 LXT97x1 JTAG Test Signal Descriptions 9781 PBGA Pin# D14 C15 B16 D15 A16 Symbol TDI TDO TMS TCK TRST Type2 I, IP O I, IP I, ID I, IP Signal Description Test Data Input. Test data sampled with respect to the rising edge of TCK. Test Data Output. Test data driven with respect to the falling edge of TCK. Test Mode Select. Test Clock. Clock input for JTAG test (REFCLK). Test Reset. Reset input for JTAG test. 1. Pin numbers apply to both the LXT9761 and the LXT9781. 2. Type Column Coding: I = Input, O = Output, IP = weak Internal Pull-up, ID = weak Internal pull-Down. 16 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Table 5. PQFP Pin#1 LXT97x1 Miscellaneous Signal Descriptions Symbol Type2 Signal Description3 Tx Output Slew Controls 0 and 1. These pins select the TX output slew rate (rise and fall time) as follows: TxSLEW_1 TxSLEW_0 0 1 0 1 Slew Rate (Rise and Fall Time) 2.5 ns 3.1 ns 3.7 ns 4.3 ns 9781 PBGA Pin# 76 77 Y8 U10 TxSLEW_0 TxSLEW_1 I 0 0 1 1 79 W10 PAUSE I Pause. Sets the default value of bit 4.10 (PAUSE). When High, the LXT97x1 advertises Pause capabilities on all ports during autonegotiation. Power-Down. When High, forces the LXT97x1 into global power-down mode. Refer to "Power-Down Mode" on page 27 for more information. Reset. This active Low input is OR'ed with the control register Reset bit (0.15). When held Low, all outputs are forced to inactive state. Address <4:0>. Sets base address. Each port adds its port number (starting with 0) to this address to determine its PHY address. 82 83 W12 V12 PWRDWN RESET I I 97 96 95 94 93 W16 V15 V13 V14 W15 ADD_4 ADD_3 ADD_2 ADD_1 ADD_0 I I I I I Port 0 Address = Base + 0. Port 1 Address = Base + 1. Port 2 Address = Base + 2. Port 3 Address = Base + 3. Port 4 Address = Base + 4. Port 5 Address = Base + 5. Port 6 Address = Base + 6 (LXT9781 Only). Port 7 Address = Base + 7 (LXT9781 Only). Bias. This pin provides bias current for the internal circuitry. Must be tied to ground through a 22.1 k 1% resistor. Quick Status. Provides continuous PHY status updates, without the need for constant polling. Quick Clock. Clock used for sending out QSTAT information. Maximum frequency is 25 MHz. 102 206 207 V17 B4 A3 RBIAS QSTAT QCLK AI O I 1. Pin numbers apply to both the LXT9761 and the LXT9781. 2. Type Column Coding: I = Input, O = Output, A = Analog, IP = weak Internal Pull-up, ID = weak Internal pull-Down. 3. The LXT97x1 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). Datasheet 17 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 6. PQFP Pin#1 LXT9761/81: 80, 88, 179 LXT9761 Only: 86 LXT97x1 Power Supply Signal Descriptions 9781 PBGA Pin# Symbol Type Signal Description A12, B11, B12, Y9, Y10, Y11 VCCD - Digital Power Supply - Core. +3.3V supply for core digital circuits. 15, 31, 52, 67, 193, 208 C4, D5, G1, M1, V1, Y6 VCCIO - Digital Power Supply - I/O Ring. +3.3V supply for digital I/O circuits. Regardless of the IO supply, digital I/O pins remain tolerant of 5V signal levels. Analog Power Supply. +3.3V supply for all analog receive circuits. LXT9761/81: 106, 113, 120, 141, 148, 155 LXT9781 Only: 127, 134 LXT9761/81: 112, 149 LXT9781 Only: 126, 135 LXT9761/81: 1, 16, 32, 48-51, 53, 68, 72-75, 81, 87, 89, 90, 91, 178, 192 LXT9781 Only: 86 103, 109, 116, 117, 123, 138, 144, 145, 152, 158 (LXT9761 and LXT9781) D17, E17, H17, J17, M17, N17, T17, U17 VCCR - A18, B18, E19, E20, K19, K20, L19, L20, T19, T20, W18, Y18 A4, B2, B8, C3, C12, D11, E2, E4, G3, G4, H2, J9 - J12, K1, K9 - K12, L9 - L12, M2, M3, M4, M9 M12, P2, T4, U5, U8, U11, V5, V11, W2, W5, W11,W13, W14, Y13, Y14, Y16, Y17 C18, D16, D18, E18, F17, F18, G17, G18, H18, J18, K17, K18, L17, L18, M18, N18, GNDA P17, P18, R17, R18, T18, U16, U18, V18, W17 Substrate Ground. Ground for chip substrate. All ground pins can be tied together using a single ground plane. Analog Ground. Ground return for analog supply. All ground pins can be tied together using a single ground plane. Digital Ground. Ground return for both core and I/O digital supplies (VCCD and VCCIO). All ground pins can be tied together using a single ground plane. VCCT Analog Power Supply. +3.3V supply for all analog transmit circuits. GNDD - 130, 131 (LXT9781 Only) 78 V10 GNDS - 1. Unless otherwise noted, pin numbers apply to both the LXT9761 and the LXT9781. 18 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Table 7. 9761 Pin# PQFP LXT97x1 LED Signal Descriptions 9781 Pin# PQFP PBGA D12 Serial LEDs 0 - 7. Each serial LED output indicates a particular status condition for every port. Bit 0 is assigned to Port 0, bit 1 to Port 1, etc. There are 8 possible LEDs per port, for a total of 48 display LEDs. However, typical equipment designs use no more than 3 LEDs per port, selected by the designer. Using per-event, rather than per-port outputs reduces the number of serial shift registers required. Instead of requiring an external serialto-parallel shift register for each port, this method requires only one per LED type, reducing board space and component costs. Refer to "Serial LED Functions" on page 38 for details. LED Clock. 1 MHz clock for LED serial data output. LED Framing. Framing signal for serial LED outputs. Port 0 LED Drivers 1 -3. These pins drive LED indicators for Port 0. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 48 on page 74 for details). Port 0 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 29 for details). Port 1 LED Drivers 1 -3. These pins drive LED indicators for Port 1. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 48 on page 74 for details). Port 1 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 29 for details). Port 2 LED Drivers 1 -3. These pins drive LED indicators for Port 2. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 48 on page 74 for details). Port 2 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 29 for details). Port 3 LED Drivers 1 -3. These pins drive LED indicators for Port 3. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 48 on page 74 for details). Port 3 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 29 for details). Symbol Type1 Signal Description2 177 176 175 174 173 172 171 170 177 176 175 174 173 172 171 170 B13 C13 A14 A13 B14 C14 A15 LEDS_0 LEDS_1 LEDS_2 LEDS_3 LEDS_4 LEDS_5 LEDS_6 LEDS_7 O 168 169 168 169 B15 D13 LEDCLK LEDLATCH O O 203 204 205 203 204 205 B5 D6 C5 LED/CFG0_1 LED/CFG0_2 LED/CFG0_3 I/OD/OS 200 201 202 200 201 202 D7 A5 C6 LED/CFG1_1 LED/CFG1_2 LED/CFG1_3 I/OD/OS 197 198 199 197 198 199 C7 A6 B6 LED/CFG2_1 LED/CFG2_2 LED/CFG2_3 I/OD/OS 186 187 188 194 195 196 A7 D8 B7 LED/CFG3_1 LED/CFG3_2 LED/CFG3_3 I/OD/OS 1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain, OS = Open Source. 2. Ports 6 and 7 are available only on the LXT9781. These pins are not bonded out on the LXT9761. Datasheet 19 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 7. 9761 Pin# PQFP LXT97x1 LED Signal Descriptions (Continued) 9781 Pin# PQFP PBGA Port 4 LED Drivers 1 -3. These pins drive LED indicators for Port 4. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 48 on page 74 for details). Port 4 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 29 for details). Port 5 LED Drivers 1 -3. These pins drive LED indicators for Port 5. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 48 on page 74 for details). Port 5 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 29 for details). Port 6 LED Drivers 1 -3. These pins drive LED indicators for Port 6. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 48 on page 74 for details). Port 6 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 29 for details). Port 7 LED Drivers 1 -3. These pins drive LED indicators for Port 7. Each LED can display one of several available status conditions as selected by the LED Configuration Register (refer to Table 48 on page 74 for details). Port 7 Configuration Inputs 1-3. When operating in Hardware Control Mode, these pins also provide configuration control options (refer to Table 9 on page 29 for details). Symbol Type1 Signal Description2 183 184 185 189 190 191 C8 A8 D9 LED/CFG4_1 LED/CFG4_2 LED/CFG4_3 I/OD/OS 180 181 182 186 187 188 D10 A9 B9 LED/CFG5_1 LED/CFG5_2 LED/CFG5_3 I/OD/OS - - - 183 184 185 A10 B10 C9 LED/CFG6_1 LED/CFG6_2 LED/CFG6_3 I/OD/OS - - - 180 181 182 C11 C10 A11 LED/CFG7_1 LED/CFG7_2 LED/CFG7_3 I/OD/OS 1. Type Column Coding: I = Input, O = Output, A = Analog, OD = Open Drain, OS = Open Source. 2. Ports 6 and 7 are available only on the LXT9781. These pins are not bonded out on the LXT9761. Table 8. Unused Pins LXT9781 PBGA Pin# A1,A2,B1,U1,U2,U3,U4, U9,V9,W1,W9, Y1,Y4,Y7 Symbol Type Signal Description LXT9761 PQFP Pin#1 25-30, 33-40, 98, 124-137, 162, 189-191, 194-196 N/C - No Connection. These pins should be left unconnected. 1. These pins are used for the two additional ports available on the LXT9781. They are not bonded out on the LXT9761. 20 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 2.0 2.1 Functional Description Introduction The LXT9781 is an eight-port Fast Ethernet 10/100 Transceiver that supports 10 Mbps and 100 Mbps networks. It complies with all applicable requirements of IEEE 802.3. The LXT9781 provides a Reduced MII (RMII) for each individual network port to interface with multiple 10/100 MACs. Each port can directly drive either a 100BASE-TX line (up to 100 meters) or a 10BASE-T line (up to 185 meters). The LXT9781 also supports 100BASE-FX operation via a Pseudo-ECL (PECL) interface. The LXT9761 offers the same features and functionality in a six-port device. This data sheet uses the singular designation "LXT97x1" to refer to both devices. 2.1.1 OSPTM Architecture Intel's LXT97x1 incorporates high-efficiency Optimal Signal ProcessingTM design techniques, combining the best properties of digital and analog signal processing to produce a truly optimal device. The receiver utilizes decision feedback equalization to increase noise and cross-talk immunity by as much as 3 dB over an ideal all-analog equalizer. Using OSP mixed-signal processing techniques in the receive equalizer avoids the quantization noise and calculation truncation errors found in traditional DSP-based receivers (typically complex DSP engines with A/D converters). The result is improved receiver noise and cross-talk performance. The OSP architecture also requires substantially less computational logic than traditional DSPbased designs. This lowers power consumption and also reduces the logic switching noise generated by DSP engines clocked at speeds up to 125 MHz. The logic switching noise can be a considerable source of EMI generated on the device's power supplies. The OSP-based LXT97x1 provides improved data recovery, EMI performance and power consumption. 2.1.2 Comprehensive Functionality The LXT97x1 performs all functions of the Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA) sublayer as defined in the IEEE 802.3 100BASE-X specification. This device also performs all functions of the Physical Media Dependent (PMD) sublayer for 100BASE-TX connections. On power-up, the LXT97x1 reads its configuration pins to check for forced operation settings. If not configured for forced operation, each port uses auto-negotiation/parallel detection to automatically determine line operating conditions. If the PHY device on the other side of the link supports auto-negotiation, the LXT97x1 will auto-negotiate with it using Fast Link Pulse (FLP) Bursts. If the PHY partner does not support auto-negotiation, the LXT97x1 will automatically detect the presence of either link pulses (10 Mbps PHY) or Idle symbols (100 Mbps PHY) and set its operating conditions accordingly. The LXT97x1 provides half-duplex and full-duplex operation at 100 Mbps and 10 Mbps. Datasheet 21 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII 2.2 2.2.1 Interface Descriptions 10/100 Network Interface The LXT97x1 supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or 100 Mbps Ethernet over fiber media (100BASE-FX). Each network interface port consists of four external pins (two differential signal pairs). The pins are shared between twisted-pair (TP) and fiber. The LXT97x1 pinout is designed to interface seamlessly with dual-high stacked RJ45 connectors. Refer to Table 3 for specific pin assignments. The LXT97x1 output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX output. When not transmitting data, the LXT97x1 generates 802.3-compliant link pulses or idle code. Input signals are decoded either as a 100BASE-TX, 100-BASE-FX, or 10BASE-T input, depending on the mode selected. Auto-negotiation/parallel detection or manual control is used to determine the speed of this interface. Figure 5. LXT97x1 Interfaces TXENn RMII DATA I/F TXDn_0 TXDn_1 RXDn_0 RXDn_1 CRS_DVn RXERn TPFOPn TPFONn TPFIPn TPFINn Network I/F MDIO Mgmt I/F MDIO MDC MDINT MDDIS VCC Port LEDs/ Hardware Control I/F LED/CFGn_n LEDS_n LEDLAT LEDCLK RBIAS 22.1k Quick Status I/F ADD<4:0> QSTAT QCLK VCCIO VCCD GNDD +3.3V +3.3V .01uF 2.2.1.1 Twisted-Pair Interface When operating at 100 Mbps, MLT3 symbols are continuously transmitted and received. When not transmitting data, the LXT97x1 generates "IDLE" symbols. During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being exchanged, the line is left in an idle state. The LXT97x1 supports either 100BASE-TX or 10BASE-T connections over 100, Category 5, Unshielded Twisted Pair (UTP). Only a transformer, series capacitors, load resistors, RJ45 and bypass capacitors are required to complete this interface. On the receive side, the internal 22 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 impedance is high enough that it has no practical effect on the external termination circuit. On the transmit side, Intel's patented waveshaping technology shapes the outgoing signal to help reduce the need for external EMI filters. Four slew rate settings (refer to Table 5 on page 17) allow the designer to match the output waveform to the magnetic characteristics. 2.2.1.2 Fiber Interface The LXT97x1 provides a PECL interface that complies with the ANSI X3.166 specification. This interface is suitable for driving a fiber-optic coupler. Fiber ports cannot be enabled via auto-negotiation; they must be enabled via the Hardware Control Interface or MDIO registers. 2.2.2 RMII Interface The LXT97x1 provides a separate RMII for each network port, each complying with the RMII standard. The RMII includes both a data interface and an MDIO management interface. 2.2.3 Configuration Management Interface The LXT97x1 provides both an MDIO Management interface and a Hardware Control interface (via the LED/CFG pins) for device configuration and management. Mode control selection is provided via the MDDIS pin as shown in Table 1. 2.2.3.1 MDIO Management Interface The LXT97x1 supports the IEEE 802.3 MII Management Interface also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the LXT97x1. The MDIO interface consists of a physical connection, a specific protocol that runs across the connection, and an internal set of addressable registers. Some registers are required and their functions are defined by the IEEE 802.3 specification. Additional registers allow for expanded functionality. Specific bits in the registers are referenced using an "X.Y" notation, where X is the register number (0-32) and Y is the bit number (0-15). The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO read and write operations are disabled and the Hardware Control Interface provides primary configuration control. When MDDIS is Low, the MDIO port is enabled for both read and write operations and the Hardware Control Interface is not used. The timing for the MDIO Interface is shown in Table 30 on page 60. MDIO read and write cycles are shown in Figure 7 (read) and Figure 8 (write). MII Addressing The protocol allows one controller to communicate with multiple LXT97x1 chips. Pins ADD_<4:0> determine the base address. Each port adds its port number (0 through 5 for the LXT9761, or 0 through 7 for the LXT9781) to the base address to obtain its port address as shown in Figure 6. Datasheet 23 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Figure 6. Port Address Scheme BASE ADDR (ex. ADDR=4) LXT9781 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 PHY ADDR (BASE+0) ex. 4 PHY ADDR (BASE+1) ex. 5 PHY ADDR (BASE+2) ex. 6 PHY ADDR (BASE+3) ex. 7 PHY ADDR (BASE+4) ex. 8 PHY ADDR (BASE+5) ex. 9 PHY ADDR (BASE+4) ex. 10 PHY ADDR (BASE+5) ex. 11 1. Ports 6 and 7 not available on the LXT9761. Figure 7. Management Interface Read Frame Structure MDC MDIO (Read) High Z 32 "1"s Preamble 0 ST 1 1 0 Op Code A4 A3 PHY Address A0 R4 R3 R0 Z 0 D15 D15D14 D14 D1 D1 D0 Data Read Idle Register Address Turn Around Write Figure 8. Management Interface Write Frame Structure MDC MDIO (Write) Idle 32 "1"s Preamble 0 ST 1 0 1 Op Code A4 A3 PHY Address A0 R4 R3 R0 1 0 Turn Around D15 D14 Data D1 D0 Idle Register Address Write 24 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 MII Interrupts The LXT97x1 provides a single interrupt pin available to all ports. Interrupt logic is shown in Figure 9. The LXT97x1 also provides two dedicated interrupt registers for each port. Register 18 provides interrupt enable and mask functions and Register 19 provides interrupt status. Setting bit 18.1 = 1, enables a port to request interrupt via the MDINT pin. An active Low on this pin indicates a status change on the LXT97x1. However, because it is a shared interrupt, it does not indicate which port is requesting service. Interrupts may be caused by any one of the following conditions: * * * * Auto-negotiation complete. Speed status change. Duplex status change. Link status change. Figure 9. Interrupt Logic Event X Enable Reg AND Event X Status Reg Per Event Force Interrupt Interrupt Enable . . . OR AND Per port . . . Port Combine Logic Interrupt Pin 1. Interrupt (Event) Status Register is cleared on read. 2. X = Any Interrupt capability 2.2.3.2 Hardware Control Interface The LXT97x1 provides a Hardware Control Interface for applications where the MDIO is not desired. The Hardware Control Interface uses the three LED driver pins for each port. 2.3 2.3.1 Operating Requirements Power Requirements The LXT97x1 requires four power supply inputs: VCCD, VCCT, VCCR, and VCCIO. The digital and analog circuits require 3.3 V supplies (VCCD, VCCT and VCCR). These inputs may be supplied from a single source although decoupling is required to each respective ground. An additional supply may be used for the RMII (VCCIO). VCCIO should be supplied from the same power source used to supply the controller on the other side of the RMII interface. Refer to Table 18 on page 53 for RMII I/O characteristics. Datasheet 25 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII As a matter of good practice, these supplies should be as clean as possible. Typical filtering and decoupling are shown in Figure 21 on page 47. 2.3.2 2.3.2.1 Clock Requirements Reference Clock The LXT97x1 requires a constant 50 MHz reference clock (REFCLK). The reference clock is used to generate transmit signals and recover receive signals. A crystal-based clock is recommended over a derived clock (i.e, PLL-based) to minmize transmit jitter. Refer to Table 19 on page 53 for clock timing requirements. 2.4 Initialization When the LXT97x1 is first powered on, reset, or encounters a link failure state, it checks the MDIO register configuration bits to determine the line speed and operating conditions to use for the network link. The configuration bits may be set by the Hardware Control or MDIO interface as shown in Figure 10. 2.4.1 MDIO Control Mode In the MDIO Control mode, the LXT97x1 reads the Hardware Control Interface pins to set the initial (default) values of the MDIO registers. Once the initial values are set, bit control reverts to the MDIO interface. 2.4.2 Hardware Control Mode In the Hardware Control Mode, LXT97x1 disables direct write operations to the MDIO registers via the MDIO Interface. On power-up or hardware reset the LXT97x1 reads the Hardware Control Interface pins and sets the MDIO registers accordingly. The following modes are available using either Hardware Control or MDIO Control: * Force network link to 100FX (Fiber). * Force network link operation to: 100TX, Full-Duplex. 100TX, Half-Duplex. 10BASE-T, Full-Duplex. 10BASE-T, Half-Duplex. * Allow auto-negotiation / parallel-detection. When the network link is forced to a specific configuration, the LXT97x1 immediately begins operating the network interface as commanded. When auto-negotiation is enabled, the LXT97x1 begins the auto-negotiation / parallel-detection operation. 26 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Figure 10. Initialization Sequence Power-up or Reset Read H/W Control Interface Initialize MDIO Registers MDIO Control Mode Low MDDIS Voltage Level? Hardware Control Mode High Pass Control to MDIO Interface (Read/Write) Disable MDIO Read and Write Operations Software Reset? Yes Reset MDIO Registers to values read at H/W Control Interface at last Hardware Reset 2.4.3 Power-Down Mode The LXT97x1 offers both global and per-port power-down modes. 2.4.3.1 Global (Hardware) Power Down The global power-down mode is controlled by PWRDWN pin 82 (PQFP) or W12 (PBGA). When PWRDWN is High, the following conditions are true: * * * * * 2.4.3.2 All LXT97x1 ports and clock are shut down. All outputs are tri-stated. All weak pad pull-up and pull-down resistors are disabled. The MDIO registers are not accessible. The MDIO registers are reset after power down. Port (Software) Power Down Individual port power-down control is provided by bit 0.11 in the respective port Control Registers (refer to Table 35 on page 65). During individual port power-down, the following conditions are true: * The individual port is shut down. * The MDIO registers remain accessible. * The MDIO registers are unaffected. Datasheet 27 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII 2.4.4 Reset The LXT97x1 provides both hardware and software resets. Configuration control of AutoNegotiation, speed and duplex mode selection is handled differently for each. During a hardware reset, settings for bits 0.13, 0.12 and 0.8 are read in from the pins (refer to Table 9 on page 29 for pin settings and to Table 35 on page 65 for register bit definitions). During a software reset (0.15 = 1), these bit settings are not re-read from the pins. They revert back to the values that were read in during the last hardware reset. Therefore, any changes to pin values made since the last hardware reset will not be detected during a software reset. During a hardware reset, register information is unavailable for 1 ms after de-assertion of the reset. During a software reset (0.15 = 1) the registers are available for reading. The reset bit should be polled to see when the part has completed reset (0.15 = 0). 2.4.5 Hardware Configuration Settings The LXT97x1 provides a hardware option to set the initial device configuration. The hardware option uses the three LED/CFG driver pins for each port. This provides three control bits per port, as listed in Table 9. The LED drivers can operate as either open drain or open source circuits as shown in Figure 11. The LED/CFG pins are sensitive to polarity and will automatically pull up or pull down to configure for either open drain or open source circuits (10 mA max current rating) as required by the hardware configuration. In applications where all ports are configured the same, several pins may be tied together with a single resistor. Note: Auto-Negotiation must be disabled before selecting fiber operation. . Figure 11. Hardware Control Settings VCC Configuration Bit = 1 LED/CFG Pin LED/CFG Pin Configuration Bit = 0 1. LEDs will automatically correct their polarity upon power-up or reset. 28 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Table 9. Hardware Configuration Settings Pin Settings LED/CFGn_1 Resulting Register Bit Values Control Register 3 0 0 Full 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 Half 100 Full Half 100 1 0 1 1 Half 10/100 Full 1 1 1 1 0 1 0 0 0 1 1 0 1 0 0 Full 1 1 0 1 0 0 1 AutoNeg 0.12 Speed 0.13 FD 0.8 0 XXXX2 Auto-Negotiation Advertisement AN Advertisement Register 100FD 4.8 100TX 4.7 10 FD 4.6 10T 4.5 Desired Configuration AutoNeg Mode Speed Mode Duplex Mode Half 1 0 2 0 10 Disabled Enabled 3 1. These pins set the default values for registers 0 and 4 accordingly. 2. X = Don't Care. 3. Do not select Fiber mode with Auto-Negotiation enabled. 2.5 2.5.1 Link Establishment Auto-Negotiation The LXT97x1 attempts to auto-negotiate with its counter-part across the link by sending Fast Link Pulse (FLP) bursts. Each burst consists of 33 link pulses spaced 62.5 s apart. Odd link pulses (clock pulses) are always present. Even link pulses (data pulses) may be present or absent to indicate a "1" or a "0". Each FLP burst exchanges 16 bits of data, which are referred to as a "page". All devices that support auto-negotiation must implement the "Base Page" defined by IEEE 802.3 (registers 4 and 5). The LXT97x1 also supports the optional `Next Page' function (registers 7 and 8). 2.5.1.1 Base Page Exchange By exchanging Base Pages, the LXT97x1 and its link partner communicate their capabilities to each other. Both sides must receive at least three identical base pages for negotiation to proceed. Each side finds the highest common capabilities that both sides support. Both sides then exchange more pages, and finally agree on the operating state of the line. 2.5.1.2 Next Page Exchange Additional information, above that required by base page exchange is also sent via "Next Pages'. The LXT97x1 fully supports the 802.3 method of negotiation via Next Page exchange. 2.5.1.3 Controlling Auto-Negotiation When auto-negotiation is controlled by software, the following steps are recommended: Datasheet 29 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII * After power-up, power-down, or reset, the power-down recovery time, (see Table 31 on page 61), must be exhausted before proceeding. * Set the auto-negotiation advertisement bits. * Enable auto-negotiation (set MDIO bit 0.12 = 1). Note: Do not enable Auto-Negotiation if fiber mode is selected. 2.5.2 Parallel Detection In parallel with auto-negotiation, the LXT97x1 also monitors for 10 Mbps Normal Link Pulses (NLP) or 100 Mbps Idle symbols. If either is detected, the device automatically reverts to the corresponding operating mode. Parallel detection allows the LXT97x1 to communicate with devices that do not support auto-negotiation. Figure 12. Auto-Negotiation Operation Power-Up, Reset, Link Failure Start Disable Auto-Negotiation 0.12 = 0 Check Value 0.12 0.12 = 1 Enable Auto-Neg/Parallel Detection Go To Forced Settings Attempt AutoNegotiation Listen for 100TX Idle Symbols Listen for 10T Link Pulses Done YES Link Set NO 2.6 RMII Operation The LXT97x1 provides an independent Reduced MII port for each network port. Each RMII uses four signals to pass received data to the MAC: RXDn<1:0>, RXERn, and CRS_DVn (where n reflects the port number). Three signals are used to transmit data from the MAC: TXDn_<1:0>, and TXENn. Both Receive and transmit signals are clocked by REFCLK. Data transmission across the RMII is implemented in di-bit pairs which equal a 4-bit-wide nibble. 30 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 2.6.1 Reference Clock The LXT97x1 requires a 50 MHz reference clock (REFCLK). The LXT97x1 samples the RMII input signals on the rising edge of REFCLK and drives RMII output signals on the falling edge. 2.6.2 Transmit Enable TXENn must be asserted and de-asserted synchronously with REFCLK. The MAC must assert TXENn the same time as the first nibble of preamble. TXENn must be de-asserted after the last bit of the packet. 2.6.3 Carrier Sense & Data Valid The LXT97x1 asserts CRS_DVn when it detects activity on the line. However, RXDn outputs zeros until the received data is decoded and available for transfer to the controller. 2.6.4 Receive Error Whenever the LXT97x1 receives an errored symbol from the network, it asserts RXERn. When it detects a bad Start-of-Stream Delimiter (SSD) it drives a "10" jam pattern on the RXD pins to indicate a false carrier event. 2.6.5 Loopback A test loopback function is available for 100 Mbps RMII testing. Bits 0.8, 0.13 and 0.14 must be set High for correct operation. When data is looped back, whatever the MAC transmits is looped back in its entirety, including the preamble. In FX mode, the respective SIGDET pin must be pulled High to enable loopback. Figure 13. Loopback Paths LXT97x1 FX Driver MII 10T Loopback Digital Block 100X Loopback Analog Block TX Driver 2.6.6 Out of Band Signalling The LXT97x1 has the capability of encoding status information in the RXData stream during IPG. Refer to the section on Monitoring Operations (page 42) for details. Datasheet 31 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII 2.6.7 4B/5B Coding Operations The 100BASE-X protocol specifies the use of a 5-bit symbol code on the network media. However, data is normally transmitted across the RMII interface in 2-bit nibblets or "di-bits". The LXT97x1 incorporates a parallel/serial converter that translates between di-bit pairs and 4-bit nibbles, and a 4B/5B encoder/decoder circuit that translates between 4-bit nibbles and 5-bit symbols for the 100BASE-X connection. Figure 14 shows the data conversion flow from nibbles to symbols. Table 10 on page 34 shows 4B/5B symbol coding (not all symbols are valid). Figure 14. RMII Data Flow Reduced MII Mode Data Flow Parallel to Serial +1 0 0 -1 0 D0 D1 D0 D1 Scramble D0 D1 D2 D3 di-bit pairs Serial to Parallel 4-bit nibbles 4B/5B S0 S1 S2 5-bit symbols S3 S4 DeScramble MLT3 Transition = 1. No Transition = 0. All transitions must follow pattern: 0, +1, 0, -1, 0, +1... 1. An independent RMII port serves each independent Network port. Network port configurations are independently selectable. 2. The Scrambler can be bypassed by setting 16.12 = 0. 2.7 2.7.1 100 Mbps Operation 100BASE-X Network Operations During 100BASE-X operation, the LXT97x1 transmits and receives 5-bit symbols across the network link. Figure 15 shows the structure of a standard frame packet. When the MAC is not actively transmitting data, the LXT97x1 sends out Idle symbols on the line. In 100TX mode, the LXT97x1 scrambles the data and transmits it to the network using MLT-3 line code. The MLT-3 signals received from the network are descrambled and decoded and sent across the RMII to the MAC. In 100FX mode, the LXT97x1 transmits and receives NRZI signals across the PECL interface. An external 100FX transceiver module is required to complete the fiber connection. As shown in Figure 15, the MAC starts each transmission with a preamble pattern. As soon as the LXT97x1 detects the start of preamble, it transmits a J/K Start of Stream Delimiter (SSD) symbol to the network. It then encodes and transmits the rest of the packet, including the balance of the preamble, the Start of Frame Delimiter (SFD), packet data, and CRC. Once the packet ends, the LXT97x1 transmits the T/R End of Stream Delimiter (ESD) symbol and then returns to transmitting Idle symbols. 32 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Figure 15. 100BASE-X Frame Format 64-Bit Preamble (8 Octets) Destination and Source Address (6 Octets each) Packet Length (2 Octets) Data Field Frame Check Field InterFrame Gap / Idle Code (4 Octets) (Pad to minimum packet size) (> 12 Octets) P0 P1 P6 SFD DA DA SA SA L1 L2 D0 D1 Dn CRC I0 IFG Replaced by /J/K/ code-groups Start-of-Stream Delimiter (SSD) Start-of-Frame Delimiter (SFD) Replaced by /T/R/ code-groups End-of-Stream Delimiter (ESD) 2.7.2 100BASE-X Protocol Sublayer Operations With respect to the 7-layer communications model, the LXT97x1 is a Physical Layer 1 (PHY) device. The LXT97x1 implements the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) sublayers of the reference model defined by the IEEE 802.3u specification. The following paragraphs discuss LXT97x1 operation from the reference model point of view. 2.7.2.1 PCS Sublayer The Physical Coding Sublayer (PCS) provides the RMII interface, as well as the 4B/5B encoding/ decoding function. For 100TX and 100FX operation, the PCS layer provides IDLE symbols to the PMD-layer line driver as long as TXEN is de-asserted. For 10T operation, the PCS layer merely provides a bus interface and serialization/de-serialization function. 10T operation does not use the 4B/5B encoder. Preamble Handling When the MAC asserts TXEN, the PCS substitutes a /J/K symbol pair, also known as the Start of Stream Delimiter (SSD), for the first two nibbles received across the RMII. The PCS layer continues to encode the remaining RMII data, following Table 10 on page 34, until TXEN is deasserted. It then returns to supplying IDLE symbols to the line driver. In the receive direction, the PCS layer performs the opposite function, substituting two preamble nibbles for the SSD. Dribble Bits The LXT97x1 handles dribbles bits in all modes. If between 1-4 dribble bits are received, the nibble will be passed across the RMII. If between 5-7 dribble bits are received, the second nibble will not be sent onto the RMII bus. Datasheet 33 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Figure 16. Protocol Sublayers MII Interface PCS Sublayer LXT97x1 Encoder/Decoder Serializer/De-serializer PMA Sublayer Link/Carrier Detect PECL Interface PMD Sublayer Scrambler/ De-scrambler Fiber Transceiver 100BASE-TX 100BASE-FX Table 10. 4B/5B Coding Code Type 4B Code 3210 0000 0001 0010 0011 0100 0101 0110 DATA 0111 1000 1001 1010 1011 1100 1101 1110 1111 1. 2. 3. 4. Name 0 1 2 3 4 5 6 7 8 9 A B C D E F 5B Code 43210 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F Interpretation The /I/ (Idle) code group is sent continuously between frames. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/. An /H/ (Error) code group is used to signal an error condition. 34 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Table 10. 4B/5B Coding (Continued) Code Type IDLE 4B Code 3210 undefined 0101 CONTROL 0101 undefined undefined undefined undefined undefined undefined INVALID undefined undefined undefined undefined undefined undefined undefined 1. 2. 3. 4. Name I1 J2 K2 T R 3 3 5B Code 43210 1 1 1 11 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Interpretation Idle. Used as inter-stream fill code Start-of-Stream Delimiter (SSD), part 1 of 2 Start-of-Stream Delimiter (SSD), part 2 of 2 End-of-Stream Delimiter (ESD), part 1 of 2 End-of-Stream Delimiter (ESD), part 2 of 2 Transmit Error. Used to force signaling errors Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid H4 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid The /I/ (Idle) code group is sent continuously between frames. The /J/ and /K/ (SSD) code groups are always sent in pairs; /K/ follows /J/. The /T/ and /R/ (ESD) code groups are always sent in pairs; /R/ follows /T/. An /H/ (Error) code group is used to signal an error condition. 2.7.2.2 PMA Sublayer Link In 100Mbps mode, the LXT97x1 establishes a link whenever the scrambler becomes locked and remains locked for approximately 50 ms. Whenever the scrambler loses lock (<12 consecutive idle symbols during a 2 ms window), the link will be taken down. This provides a very robust link, essentially filtering out any small noise hits that may otherwise disrupt the link. Furthermore 100M idle patterns will not bring up a 10M link. The LXT97x1 reports link failure via the RMII status bits (1.2, 17.10, and 19.4) and interrupt functions. If auto-negotiate is enabled, link failure causes the LXT97x1 to re-negotiate. Link Failure Override The LXT97x1 will normally transmit 100 Mbps data packets or Idle symbols only if it detects the link is up, and transmits only FLP bursts if the link is not up. Setting bit 16.14 = 1 overrides this function, allowing the LXT97x1 to transmit data packets even when the link is down. This feature is provided as a diagnostic tool. Note that auto-negotiation must be disabled to transmit data packets in the absence of link. If auto-negotiation is enabled, the LXT97x1 will automatically begin transmitting FLP bursts if the link goes down. Datasheet 35 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Carrier Sense/Data Valid The LXT97x1 asserts CRS_DV whenever the respective port receiver is non-idle (as defined by the RMII Specification Revision 1.2), including false carrier events. Assertion of CRS_DV is asynchronous with respect to REFCLK. In the event that signal decoding is not complete when CRS_DV is asserted, the LXT97x1 outputs 00 on the RXD1:0 lines until the decoded data is available. When the line returns to an idle state CRS_DV is de-asserted, asynchronously with respect to REFCLK. In the event that the FIFO still contains data to be passed to the MAC via the RMII when CRS is de-asserted, CRS_DV will toggle on nibble boundaries until the FIFO is empty. For 100BASE-X signals, CRS_DV toggles at 25 MHz. For 10BASE-T signals, CRS_DV toggles at 2.5 MHz. 2.7.2.3 Twisted-Pair PMD Sublayer The twisted-pair Physical Medium Dependent (PMD) layer provides the signal scrambling and descrambling, line coding and decoding (MLT-3 for 100TX, Manchester for 10T), as well as receiving, polarity correction, and baseline wander correction functions. Scrambler/Descrambler (100TX Only) The purpose of the scrambler is to spread the signal power spectrum and further reduce EMI using an 11-bit, non-data-dependent polynomial. The receiver automatically decodes the polynomial whenever IDLE symbols are received. The scrambler/descrambler can be bypassed by setting bit 16.12 = 1. The scrambler is automatically bypassed when the fiber port is enabled. Scramber bypass is provided for diagnostic and test support. Baseline Wander Correction (100TX Only) The LXT97x1 provides a baseline wander correction function which makes the device robust under all network operating conditions. The MLT3 coding scheme used in 100BASE-TX is by definition "unbalanced". This means that the DC average value of the signal voltage can "wander" significantly over short time intervals (tenths of seconds). This wander can cause receiver errors, particularly in less robust designs, at long line lengths (100 meters). The exact characteristics of the wander are completely data dependent. The LXT97x1 baseline wander correction characteristics allow the device to recover error-free data while receiving worst-case "killer" packets over all cable lengths. Polarity Correction The LXT97x1 automatically detects and corrects for the condition where the receive signal (TPFIP/N) is inverted. Reversed polarity is detected if eight inverted link pulses, or four inverted End-of-Frame (EOF) markers, are received consecutively. If link pulses or data are not received by the maximum receive time-out period, the polarity state is reset to a non-inverted state. 36 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 2.7.2.4 Fiber PMD Sublayer The LXT97x1 provides a PECL interface for connection to an external fiber-optic transceiver. (The external transceiver provides the PMD function for fiber media.) The LXT97x1 uses an NRZI format and operates at 100 Mbps. The LXT97x1 does not support 10FL applications. Signal Fault Indications The LXT97x1 Signal Detect pins receive signal fault indications from local fiber transceivers via the SD pins. The device can also detect far end fault code in the received data stream. The LXT97x1 "ORs" both fault conditions to set bit 1.4. Bit 1.4 is set once and clears when read. Either fault condition causes the LXT97x1 to drop the link unless Forced Link Pass is selected (16.14 = 1). Link down condition is then reported via interrupts and status bits. In response to locally detected signal faults (SD activated by the local fiber transceiver), the affected port can transmit the far end fault code if fault code transmission is enabled by bit 16.2. * When bit 16.2 = 1, transmission of the far end fault code is enabled. The LXT97x1 transmits far end fault code if fault conditions are detected by the Signal Detect pins. * When bit 16.2 = 0, the LXT97x1 does not transmit far end fault code. It continues to transmit idle code and may or may not drop link depending on the setting for bit 16.14. 2.8 10 Mbps Operation The LXT97x1 will operate as a standard 10BASE-T transceiver and supports all the standard 10 Mbps functions. During 10BASE-T (10T) operation, the LXT97x1 transmits and receives Manchester-encoded data across the network link. When the MAC is not actively transmitting data, the LXT97x1 sends out link pulses on the line. In 10T mode, the polynomial scrambler/descrambler is inactive. Manchester-encoded signals received from the network are decoded by the LXT97x1 and sent across the RMII to the MAC. The 10M reversed polarity correction function is the same as the 100M function described on page 36. The LXT97x1 does not support fiber connections at 10 Mbps. 2.8.1 Preamble Handling The LXT97x1 offers two options for preamble handling, selected by bit 16.5. In 10T Mode when 16.5 = 0, the LXT97x1 strips the entire preamble off of received packets. CRS_DV is asserted coincident with SFD. CRS_DV is held Low for the duration of the preamble. When CRS_DV is asserted, the very first two nibbles driven by the LXT97x1 are the SFD "5D" hex followed by the body of the packet. In 10T mode with 16.5 = 1, the LXT97x1 passes the preamble through the RMII and asserts CRS_DV simultaneously. Datasheet 37 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII 2.8.2 Dribble Bits The LXT97x1 device handles dribbles bits in all modes. If between 1-4 dribble bits are received, the nibble will be passed across the RMII, padded with 1s if necessary. If between 5-7 dribble bits are received, the second nibble will not be sent onto the RMII bus. 2.8.3 Link Test In 10T mode, the LXT97x1 always transmit link pulses. If the link test function is enabled, it monitors the connection for link pulses. Once link pulses are detected, data transmission will be enabled and will remain enabled as long as either the link pulses or data transmission continue. If the link pulses stop, the data transmission will be disabled. If the link test function is disabled, the LXT97x1 will transmit to the connection regardless of detected link pulses. The link test function can be disabled by setting bit 16.14 = 1. 2.8.3.1 Link Failure Link failure occurs if Link Test is enabled and link pulses or packets stop being received. If this condition occurs, the LXT97x1 returns to the auto-negotiation phase if auto-negotiation is enabled. 2.8.4 Jabber If a transmission exceeds the jabber timer, the LXT97x1 will disable the transmit and loopback functions. The RMII does not include a Jabber pin, however the MAC may read Register 1 to determine Jabber status. The LXT97x1 automatically exits jabber mode after the unjab time has expired. This function can be disabled by setting bit 16.10 = 1. 2.9 2.9.1 Monitoring Operations Monitoring Auto-Negotiation Auto-negotiation can be monitored as follows: * Bits 1.2 and 17.10 = 1 once the link is established. * Additional bits in Register 1 (refer to Table 36 on page 65) and Register 17 (refer to Table 45 on page 71) can be used to determine the link operating conditions and status. 2.9.2 Serial LED Functions The LXT97x1 provide eight serial LED outputs (LEDS7:0) which may be attached to external HC595-type shift registers (refer to Figure 25 on page 51). The LEDCLK signal is used to shift data into the 595's internal shift register. The LEDLATCH signal is used to load data from the 595's internal shift register to the 595's internal storage register. The LXT97x1 drives the LEDSn and LEDLATCH outputs on the falling edge of LEDCLK. All serial LEDs will be stretched in accordance with 20.1 & 20.3:2. 38 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Each serial output reports a specific status condition for all ports. Ports 0 through 7 are assigned bits 0:7 in each stream (bits 3 and 4 are not used on the LXT9761). Serial outputs report the following conditions for each port: * LEDS0 Serial Output indicates Activity. 0 = Active1 = Inactive * LEDS1 Serial Output indicates Polarity 0 = Switched Polarity1 = Normal Polarity * LEDS2 Serial Output indicates Duplex (D). 0 = Full Duplex1 = Half Duplex * LEDS3 Serial Output indicates Link. 0 = Link active1 = Link inactive * LEDS4 Serial Output indicates Collision. 0 = Collision active1 = Collision inactive * LEDS5 Serial Output indicates Receive. 0 = Receive active1 = Receive inactive * LEDS6 Serial Output indicates Transmit. 0 = Transmit active1 = Transmit inactive * LEDS7 Serial Output indicates Speed. 0 = 100 Mbps1 = 10 Mbps Figure 17. Serial LED Streams LEDCLK (1 MHz) LEDS(0) LEDS(1) LEDS(2) LEDS(3) LEDS(4) LEDS(5) activity (port 0) activity (port 1) activity (port 2) polarity (port 2) activity (port 3) activity (port 4) polarity (port 4) activity (port 5) activity (port 6) activity (port 7) activity (port 0) activity (port 1) activity (port 2) activity (port 3) activity (port 4) activity (port 5) polarity (port 0) polarity (port 1) polarity (port 3) polarity (port 5) polarity (port 6) polarity (port 7) polarity (port 0) polarity (port 1) polarity (port 2) polarity (port 3) polarity (port 4) polarity (port 5) duplex (port 0) duplex (port 1) duplex (port 2) duplex (port 3) duplex (port 4) duplex (port 5) duplex (port 6) duplex (port 7) duplex (port 0) duplex (port 1) duplex (port 2) duplex (port 3) duplex (port 4) duplex (port 5) link (port 0) link (port 1) link (port 2) link (port 3) link (port 4) link (port 5) link (port 6) link (port 7) link (port 0) link (port 1) link (port 2) link (port 3) link (port 4) link (port 5) collision (port 0) collision collision (port 1) (port 2) collision collision collision collision collision (port 3) (port 4) (port 5) (port 6) (port 7) collision collision collision collision (port 0) (port 1) (port 2) (port 3) collision collision (port 4) (port 5) receive (port 0) receive (port 1) receive (port 2) receive (port 3) receive (port 4) receive (port 5) receive (port 6) receive (port 7) receive (port 0) receive (port 1) receive (port 2) receive (port 3) receive (port 4) receive (port 5) LEDS(6) LEDS(7) LEDLATCH transmit (port 0) speed (port 0) transmit transmit transmit transmit transmit transmit transmit (port 1) (port 2) (port 3) (port 4) (port 5) (port 6) (port 7) transmit transmit transmit (port 0) (port 1) (port 2) transmit transmit transmit (port 3) (port 4) (port 5) speed (port 1) speed (port 2) speed (port 3) speed (port 4) speed (port 5) speed (port 6) speed (port 7) speed (port 0) speed (port 1) speed (port 2) speed (port 3) speed (port 4) speed (port 5) Spare on LXT9761 Spare on LXT9761 Alternate Port Positions for LXT9761 LEDS(0:7) Port 5 Port 0 Port 1 Port 2 Spare Spare Port 3 Port 4 Port 5 Port 0 Port 1 Port 2 Spare Spare Port 3 Datasheet 39 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII 2.9.3 Per-Port LED Driver Functions The LXT97x1 incorporates three direct drive LEDs per port. On power up all the LEDs will light for approximately 1 second after reset de-asserts. Each LED can be programmed to one of several different display modes using the LED Configuration Register. Each per-port LED can be programmed (refer to Table 48 on page 74) to indicate one the following conditions: * * * * * * Operating Speed. Transmit Activity. Receive Activity. Collision Condition. Link Status. Duplex Mode. The LEDs can also be programmed to display various combined status conditions. For example, setting bits 20.15:12 = 1101 produces the following combination of Link and Activity indications: * If Link is down LED is off. * If Link is up LED is on. * If Link is up AND activity is detected, the LED will blink at the stretch interval selected by bits 20.3:2 and will continue to blink as long as activity is present. The LED/CFG driver pins are also used to provide initial configuration settings. The LED pins are sensitive to polarity and will automatically pull up or pull down to configure for either open drain or open source circuits (10mA max current rating) as required by the hardware configuration. Refer to the discussion of "Hardware Control Interface" on page 25 for details. 2.9.3.1 LED Pulse Stretching The LED Configuration Register also provides optional LED pulse stretching to 30, 60, or 100 ms. If during this pulse stretch period, the event occurs again, the pulse stretch time will be further extended. When an event such as receiving a packet occurs it will be edge detected and it will start the stretch timer. The LED driver will remain asserted until the stretch timer expires. If another event occurs before the stretch timer expires then the stretch timer will be reset and the stretch time will be extended. When a long event (such as duplex status) occurs it will be edge detected and it will start the stretch timer. When the stretch timer expires the edge detector will be reset so that a long event will cause another pulse to be generated from the edge detector which will reset the stretch timer and cause the LED driver to remain asserted. Figure 18 shows how the stretch operation functions. 40 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Figure 18. LED Pulse Stretching Event LED stretch stretch stretch Note: The direct drive LED outputs in this diagram are shown as active Low. 2.9.4 Using the Quick Status Register The LXT97x1 continuously sends out the Quick Status Register (Address 17) contents on the QSTAT pin. This output provides a continuous, real-time status update of several different LXT97x1 attributes and modes. The information can be used to sense RX, TX, COL and to monitor the status and speed of the auto-negotiation process. A simple signature is used to delineate the start of the QSTAT register information allowing a very simple interface to be designed. The 16 bits of the Quick Status Register are separated by a 16-bit signature frame (1111111111111111). The LXT97x1 sources this status information separated by the signature with respect to the falling edge of the QCLK input. This allows an ASIC to provide only 1 clock output for multiple PHY devices. The ASIC can also select a frequency up to 25 MHz to operate this interface. Refer to Table 45 on page 71 for Quick Status bits descriptions. Figure 19. Quick Status Register 16 BIT SIGNATURE QSTAT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 QUICK STATUS REGISTER-Port 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (0) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 (0) D3 D2 D1 D0 Port 2 thru n-1 QUICK STATUS REGISTER-Port n D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (0) 1. QCLK is used to output the above information. 2. Bits D15 and D0 are always set to 0. (0) Datasheet 41 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII 2.9.5 Out-of-Band Signalling The LXT97x1 provides an out-of-band signalling option to transfer status information across the RMII receive interface. Enabled when 25.0=1, this feature uses the RXD(1:0) data bus during the IPG time as shown in Figure 20. The two status bits that are transferred across the RXD bus are software selectable via Register 25 (refer to Table 49 on page 75). In normal operation the LXT97x1 stuffs the RXD bus with zeros during the Inter-Packet Gap (IPG). A software-selectable bit enables the RMII out of band signalling feature. Once this bit is set the LXT97x1 replaces those zeros with the selected status bits during the IPG. Figure 20. RMII Programmable Out of Band Signalling REFCLK CRS_DV RXD(1) status 1 status 1 0s data data data data status 1 status 1 status 1 status 1 status 1 RXD(0) status 0 status 0 0s data data data data status 0 status 0 status 0 status 0 status 0 1. When network activity is detected, the LXT97x1 asserts CRS_DV asynchronously with respect to REFCLK. 2. After CRS_DV is asserted, the LXT97x1 will zero-stuff the RXData bits until the received data has been processed through the FIFO. 3. When network activity ceases, the LXT97x1 de-asserts CRS_DV synchronously with respect to REFCLK. CRS_DV will toggle until all data in the FIFO has been processed through the RMII. Once the FIFO is empty, the LXT97x1 will drive the status bits selected by the Out-of-Band Signalling Register (refer to Table 49 on page 75) on the RXD outputs. 2.10 Boundary Scan (JTAG1149.1) Functions The LXT97x1 includes a IEEE 1149.1 boundary scan test port for board level testing. All digital input, output, and input/output pins are accessible. 2.10.1 Boundary Scan Interface This interface consists of five pins (TMS,TDI,TDO, TCK and TRST). It includes a state machine, data register array, and instruction register. The TMS and TDI pins are internally pulled up. TCK is internally pulled down. TDO does not have an internal pull-up or pull-down. 2.10.2 State Machine The TAP controller is a 16 Bit state machine driven by the TCK and TMS pins. Upon reset the TEST_LOGIC_RESET state is entered. The state machine is also reset when TMS is high for five TCK periods. 42 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 2.10.3 Instruction Register After the state machine resets, the IDCODE instruction is always invoked. The decode logic ensures the correct data flow to the Data registers according to the current instruction. Valid instructions are listed in Table 12. 2.10.4 Boundary Scan Register Each BSR cell has two stages. A flip-flop and a latch are used for the serial shift stage and the parallel output stage. There are four modes of operation as listed in Table 11. Table 11. BSR Mode of Operation Mode 1 2 3 4 Description Capture Shift Update System Function Table 12. Supported JTAG Instructions Name EXTEST IDCODE SAMPLE High Z Clamp BYPASS Code 0000000000000000 1111111111111110 1111111111111110 1111111111001111 1111111111101111 1111111111111111 Description External Test ID Code Inspection Sample Boundary Force Float Clamp Bypass Scan BSR ID REG BSR Bypass BSR Bypass Data Register Table 13. Device ID Register 31:28 Version 0000 27:12 Part ID (hex) 2621 (LXT9761) 2635 (LXT9781) 11:8 Jedec Continuation Characters 0000 7:1 JEDEC ID1 111 1110 0 Reserved 1 1. The JEDEC ID is an 8-bit identifier. The MSB is for parity and is ignored. Intel's JEDEC ID is FE (1111 1110) which becomes 111 1110. Datasheet 43 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII 3.0 3.1 Application Information Design Recommendations The LXT97x1 is designed to comply with IEEE requirements and to provide outstanding receive Bit Error Rate (BER) and long-line-length performance. To achieve maximum performance from the LXT97x1, attention to detail and good design practices are required. Refer to the LXT97x1 Design and Layout Guide for detailed design and layout information. 3.1.1 General Design Guidelines Adherence to generally accepted design practices is essential to minimize noise levels on power and ground planes. Up to 50 mV of noise is considered acceptable. 50 to 80 mV of noise is considered marginal. High-frequency switching noise can be reduced, and its effects can be eliminated, by following these simple guidelines throughout the design: * Fill in unused areas of the signal planes with solid copper and attach them with vias to a VCC or ground plane that is not located adjacent to the signal layer. * Use ample bulk and decoupling capacitors throughout the design (a value of .01 F is recommended for decoupling caps). * * * * * * Provide ample power and ground planes. Provide termination on all high-speed switching signals and clock lines. Provide impedance matching on long traces to prevent reflections. Route high-speed signals next to a continuous, unbroken ground plane. Filter and shield DC-DC converters, oscillators, etc. Do not route any digital signals between the LXT97x1 and the RJ45 connectors at the edge of the board. edge of the board. Use this area for chassis ground, or leave it void. * Do not extend any circuit power and ground plane past the center of the magnetics or to the 3.1.2 Power Supply Filtering Power supply ripple and digital switching noise on the VCC plane can cause EMI problems and degrade line performance. The best approach is to minimize ground noise as much as possible using good general techniques and by filtering the VCC plane. It is generally difficult to predict in advance the performance of any design, although certain factors greatly increase the risk of having problems: * Poorly-regulated or over-burdened power supplies * Wide data busses (32-bits+) running at a high clock rate * DC-to-DC converters 44 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Intel recommends filtering the power supply to the analog VCC pins of the LXT97x1. This has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT97x1, which helps line performance. Second, if the VCC planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing EMI problems. The recommended implementation is to break the VCC plane into two sections. The digital section supplies power to the VCCD and VCCIO pins of the LXT97x1. The analog section supplies power to the VCCA pins. The break between the two planes should run underneath the device. In designs with more than one LXT97x1, a single continuous analog VCC plane can be used to supply them all. The digital and analog VCC planes should be joined at one or more points by ferrite beads. The beads should produce at least a 100 impedance at 100 MHz. Beads should be placed so that current flow is evenly distributed. The maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. A bulk cap (2.2 -10 uF) should be place on each side of each bead. In addition, a high-frequency bypass cap (.01uf) should be placed near each analog VCC pin. 3.1.3 Power and Ground Plane Layout Considerations Great care needs to be taken when laying out the power and ground planes. * Follow the guidelines in the LXT97x1 Design and Layout Guide for locating the split between the digital and analog VCC planes. * Keep the digital VCC plane away from the TPFOP/N and TPFIP/N signals, away from the magnetics, and away from the RJ45 connectors. * Place the layers so that the TPFOP/N and TFPIP/N signals can be routed near or next to the ground plane. For EMI reasons, it is more important to shield TPFOP/N than TPFIP/N. 3.1.3.1 Chassis Ground For ESD reasons, it is a good design practice to create a separate chassis ground that encircles the board and is isolated via moats and keep-out areas from all circuit-ground planes and active signals. Chassis ground should extend from the RJ-45 connectors to the magnetics, and can be used to terminate unused signal pairs (`Bob Smith' termination). In single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2kV isolation capacitor. In multi-point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2kV isolation to the Bob Smith termination. 3.1.4 RMII Terminations Series termination resistors are not typically required on the RMII signals driven by the LXT97x1. 3.1.5 The RBIAS Pin The LXT97x1 requires a 22.1 k, 1% resistor directly connected between the RBIAS pin and ground. Place the RBIAS resistor as close to the RBIAS pin as possible. Run an etch directly from the pin to the resistor, and sink the other side of the resistor to a filtered ground. Surround the RBIAS trace with a filtered ground; do not run high-speed signals next to RBIAS. Datasheet 45 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII 3.1.6 The Twisted-Pair Interface Follow standard guidelines for a twisted-pair interface: * * * * * Place the magnetics as close as possible to the LXT97x1. Keep transmit pair traces as short as possible; both traces should have the same length. Avoid vias and layer changes as much as possible. Keep the transmit and receive pairs apart to avoid cross-talk. Route the transmit pair adjacent to a ground plane. The optimum arrangement is to place the transmit traces two to three layers from the ground plane, with no intervening signals. to supply center tap current to all ports. All ports draw a combined total of 505 mA so the bead should be rated at 760 mA. * Improve EMI performance by filtering the TPO center tap. A single ferrite bead may be used 3.1.6.1 Magnetics Information The LXT97x1 requires a 1:1 ratio for the receive transformers and a 1:1 ratio for the transmit transformers. The transformer isolation voltage should be rated at 1.5 kV to protect the circuitry from static voltages across the connectors and cables. Refer to Table 14 for transformer requirements. Before committing to a specific component, designers should contact the manufacturer for current product specifications, and validate the magnetics for the specific application. 3.1.7 The Fiber Interface The fiber interface consists of a PECL transmit and receive pair to an external fiber-optic transceiver. The transmit and receive pair should be DC-coupled to the transceiver, and biased appropriately. Refer to the fiber transceiver manufacturer's recommendations for termination circuitry. Figure 23 on page 49 shows a typical example. Table 14. Magnetics Requirements Parameter Rx turns ratio Tx turns ratio Insertion loss Primary inductance Transformer isolation Differential to common mode rejection Min - - 0.0 350 - 40 35 -16 Return Loss -10 - - dB 80 MHz Nom 1:1 1:1 0.6 - 1.5 - - - Max - - 1.1 - - - - - Units - - dB Test Condition H kV dB dB dB .1 to 60 MHz 60 to 100 MHz 30 MHz 3.2 Typical Application Circuits Figure 21 through Figure 25 show typical application circuits. 46 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Figure 21. Power and Ground Supply Connections LXT97x1 GNDS RBIAS GNDA .01F .01F 22.1 k 1% VCCT VCCR Analog Supply Plane Ferrite Bead 10F + Digital Supply Plane + 10F VCCD .01F +3.3V GNDD 10F .01F VCCIO + +3.3V Datasheet 47 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Figure 22. Typical Twisted-Pair Interface TPFOP 1:1 RJ45 1 1 2 3 TPFON TPFIP 270 pF 5% 1:1 50 1% 50 50 4 50 5 6 LXT97x1 TPFIN 2 50 1% 50 50 7 50 8 270 pF 5% 0.01 F 3 * * * = 0.001 F / 2.0 kV 4 VCCT 0.1F .01F GNDA 5 1. The 100 transmit load termination resistor typically required is integrated in the LXT97xx. 2. Magnetics without a receive pair center-tap do not require a 2 kV termination. 3. Center tap current may be supplied from 3.3V VCCA as shown. However, additional power savings may be realized by supplying the center-tap from from a 2.5V current source. In either case a single ferrite bead (rated at 800 mA) may be used to supply center tap current to all ports. 4. Receive common mode bypass cap may improve BER performance in systems with noisy power supplies. 5. Recommended 0.1F capacitor to improve the EMI performance. 48 To Twisted-Pair Network Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Figure 23. Typical Fiber Interface VCCD +3.3V 16 50 50 0.1 mF GNDD TPFONn TPFOPn VCCD +3.3V TDTD+ To Fiber Network LXT97x1 130 Fiber Txcvr SD 82 GNDD 130 130 VCCD +3.3V 0.1 mF GNDD SD/TPn 1 TPFINn TPFIPn 82 82 RDRD+ GNDD 1. Refer to fiber transceiver manufacturer's recommendations for termination circuitry. Example shown above is suitable for HFBR5900-series devices. Datasheet 49 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Figure 24. Typical RMII Interface 8 Port MAC TxData 8 8 8 LXT9781 TXDn_0 TXDn_1 TXENn RXDn_0 RXDn_1 RXERn CRS_DVn REFCLK Magnetics/Fiber Transceiver 8 RxData 8 8 8 SysCLK 50MHz System Clock from Switch ASIC or external source 50 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Figure 25. Typical Serial LED Interface LEDLATCH 595 rclk Qa srclk ser Qh 595 LXT9781 LEDCLK LEDS(0) activity(7) activity(6) activity(5) activity(4) activity(3) activity(2) activity(1) activity(0) 595 LEDLATCH LEDCLK rclk Qa srclk leds(4) ser Qh collision(7) collision(6) collision(5) collision(4) collision(3) collision(2) collision(1) collision(0) See Detail for LXT9761 configuration. LEDLATCH LEDCLK LEDS(1) rclk srclk ser Qa Qh polarity(7) polarity(6) polarity(5) polarity(4) polarity(3) polarity(2) polarity(1) polarity(0) 595 LEDLATCH LEDCLK LEDS(5) rclk Qa srclk ser Qh receive(7) receive(6) receive(5) receive(4) receive(3) receive(2) receive(1) receive(0) 595 LEDLATCH LEDCLK LEDS(2) rclk Qa srclk ser Qh duplex(7) duplex(6) duplex(5) duplex(4) duplex(3) duplex(2) duplex(1) duplex(0) 595 LEDLATCH LEDCLK LEDS(6) rclk Qa srclk ser Qh transmit(7) transmit(6) transmit(5) transmit(4) transmit(3) transmit(2) transmit(1) transmit(0) 595 LEDLATCH LEDCLK LEDS(3) rclk Qa srclk ser Qh link(7) link(6) link(5) link(4) link(3) link(2) link(1) link(0) 595 LEDLATCH LEDCLK LEDS(7) rclk Qa srclk ser Qh speed(7) speed(6) speed(5) speed(4) speed(3) speed(2) speed(1) speed(0) Alternate Configuration for LXT9761 LEDLATCH LEDCLK 595 rclk Qa srclk ser Qh 1. Note: The outputs are always enabled on the 595 chips. 2. Ports 6 and 7 are not available on the LXT9761. Serial outputs are re-mapped as shown in Detail at right. LEDS(0) activity(5) activity(4) activity(3) Not Used Not Used activity(2) activity(1) activity(0) Datasheet 51 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII 4.0 Note: Test Specifications Table 15 through Table 31 and Figure 26 through Figure 36 represent the performance specifications of the LXT97x1. These specifications are guaranteed by test, except where noted "by design." Minimum and maximum values listed in Table 17 through Table 31 apply over the recommended operating conditions specified in Table 16. Table 15. Absolute Maximum Ratings Parameter Supply voltage Operating temperature Ambient Case Storage temperature Sym VCC TOPA TOPC TST Min -0.3 -15 - -65 Max TBD +85 +120 +150 Units V C C C Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 16. Operating Conditions Parameter Ambient Recommended operating temperature Case Recommended supply voltage2 VCC current Analog & Digital I/O 100BASE-TX 100BASE-FX 10BASE-T Power-Down Mode Auto-Negotiation3 TOPC Vcca, Vccd Vccio ICC ICC ICC ICC ICC 0 3.15 3.15 - - - - - - - - 1183 - 118 25 114.53 3 Sym TOPA Min 0 Typ1 - Max 70 110 3.45 3.45 1383 - 138 - 1383 3 Units C C V V mA mA mA mA mA 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Voltages with respect to ground unless otherwise specified. 3. Per-port @ 3.3V. Table 17. Digital I/O Characteristics 1 Parameter Input Low voltage3 Input High voltage3 Sym VIL VIH Min - 2.0 Typ2 - - Max 0.8 - Units V V Test Conditions - - 1. Applies to all pins except RMII pins. Refer to Table 18 for RMII I/O Characteristics. 2. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 3. Does not apply to REFCLK. Refer to Table 19 for clock input levels. 52 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Table 17. Digital I/O Characteristics 1 (Continued) Parameter Input current Output Low voltage Output High voltage Sym II VOL VOH Min -100 - 2.4 Typ2 - - - Max 100 0.4 - Units Test Conditions 0.0 < VI < VCC IOL = 4 mA IOH = -4 mA A V V 1. Applies to all pins except RMII pins. Refer to Table 18 for RMII I/O Characteristics. 2. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 3. Does not apply to REFCLK. Refer to Table 19 for clock input levels. Table 18. Digital I/O Characteristics - RMII Pins Parameter Input Low voltage Input High voltage Input current Output Low voltage Output High voltage Driver output resistance (Line driver output enabled) Sym VIL VIH II VOL VOH RO1 RO 1 Min - 2.0 -100 - 2.2 - - Typ2 - - - - - 100 100 Max 0.8 - 100 0.4 - - - Units V V Test Conditions - - 0.0 < VI < VCC IOL = 4 mA IOH = -4 mA, VCC = 3.3V VCC = 2.5V VCC = 3.3V A V V 1. Parameter is guaranteed by design; not subject to production testing. 2. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Table 19. Required Clock Characteristics Parameter Input Low voltage Input High voltage Input frequency Input clock frequency tolerance1 Input clock duty cycle 1 Sym VIL VIH F Min - 2.0 - - 35 Typ2 - - 50 - 50 Max 0.8 - - 50 65 Units V V MHz ppm % Test Conditions - - - - - f Tdc 1. Parameter is guaranteed by design; not subject to production testing. 2. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Table 20. 100BASE-TX Transceiver Characteristics Parameter Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Sym VP Vss TRF Min 0.95 98 3.0 Typ1 - - - Max 1.05 102 5.0 Units V % ns Test Conditions Note 2 Note 2 Note 2 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Measured at the line side of the transformer, line replaced by 100(+/-1%) resistor. Datasheet 53 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 20. 100BASE-TX Transceiver Characteristics (Continued) Parameter Rise/fall time symmetry Duty cycle distortion Overshoot Sym TRFS - VO Min - - - Typ1 - - - Max 0.5 0.5 5 Units ns ns % Test Conditions Note 2 Offset from 16ns pulse width at 50% of pulse peak - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Measured at the line side of the transformer, line replaced by 100(+/-1%) resistor. Table 21. 100BASE-FX Transceiver Characteristics Parameter Sym Min Typ1 Transmitter Peak differential output voltage (single ended) Signal rise/fall time Jitter (measured differentially) VOP TRF - 0.6 - - - - - Receiver Peak differential input voltage Common mode input range VIP VCMIR 0.55 - - - 1.5 VCC - 0.7 V V - - 1.5 1.9 1.4 V ns ns 10 <-> 90% - - 2.0 pF load Max Units Test Conditions 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Table 22. 10BASE-T Transceiver Characteristics Parameter Sym Min Typ1 Transmitter Peak differential output voltage Link transmit period Transmit timing jitter added by the MAU and PLS sections 3, 4 VOP - - 2.2 8 0 2.5 - - Receiver Link min receive timer Link max receive timer Time link loss receive Differential squelch threshold 1. 2. 3. 4. 5. TLRmin TLRmax TLL VDS 2 50 50 - 4 64 64 390 7 150 150 - ms ms ms mV Peak - - - 5 MHz square wave input 2.8 24 11 V ms ns Note 2 - Note 5 Max Units Test Conditions Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Measured at the line side of the transformer, line replaced by 100(+/-1%) resistor. Parameter is guaranteed by design; not subject to production testing. IEEE 802.3 specifies maximum jitter addition at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU. After line model specified by IEEE 802.3 for 10BASE-T MAU 54 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Figure 26. 100BASE-TX Receive Timing REFCLK t1 RXD(1:0) t2 TPFI t3 t4 CRS_DV Table 23. 100BASE-TX Receive Timing Parameters Parameter RXD<1:0>, CRS_DV, RXER setup to REFCLK rising edge RXD<1:0>, CRS_DV, RXER hold from REFCLK rising edge Receive start of "J" to CRS_DV asserted Receive start of "T" to CRS_DV de-asserted Sym t1 t2 t3 t4 Min 4 2 - - Typ1 - - 14 22 Max - - - - Units ns ns BT BT Test Conditions - - - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Figure 27. 100BASE-TX Transmit Timing REFCLK t1 TXD(1:0) t2 TPFO t4 t3 t5 TX_EN Datasheet 55 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 24. 100BASE-TX Transmit Timing Parameters Parameter TXD<1:0> setup to REFCLK rising edge TXD<1:0> hold from REFCLK rising edge TX_EN sampled to TPFO out (Tx latency) TX_EN setup to REFCLK rising edge TX_EN hold from REFCLK rising edge Sym t1 t2 t3 t4 t5 Min 4 2 - 4 2 Typ1 - - 13 - - Max - - - - - Units ns ns BT ns ns Test Conditions - - - - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Figure 28. 100BASE-FX Receive Timing REFCLK t1 RXD(1:0) t2 TPFI t3 t4 CRS_DV Table 25. 100BASE-FX Receive Timing Parameters Parameter RXD<1:0>, CRS_DV, RXER setup to REFCLK rising edge RXD<1:0>, CRS_DV, RXER hold from REFCLK rising edge Receive start of "J" to CRS_DV asserted Receive start of "T" to CRS_DV de-asserted Sym t1 t2 t3 t4 Min 4 2 - - Typ1 - - 12 20 Max - - - - Units ns ns BT BT Test Conditions - - - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 56 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Figure 29. 100BASE-FX Transmit Timing REFCLK t1 TXD(1:0) t2 TPFO t4 t3 t5 TX_EN Table 26. 100BASE-FX Transmit Timing Parameters Parameter TXD<1:0> setup to REFCLK rising edge TXD<1:0> hold from REFCLK rising edge TX_EN sampled to TPFO out (Tx latency) TX_EN setup to REFCLK rising edge TX_EN hold from REFCLK rising edge Sym t1 t2 t3 t4 t5 Min 4 2 - 4 2 Typ1 - - 13 - - Max - - - - - Units ns ns BT ns ns Test Conditions - - - - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Figure 30. 10BASE-T Receive Timing REFCLK t1 RXD(1:0) t2 TPFI t3 t4 CRS_DV Datasheet 57 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 27. 10BASE-T Receive Timing Parameters Parameter RXD<1:0>, CRS_DV setup to REFCLK rising edge RXD<1:0>, RX_DV hold from REFCLK rising edge TPFI in to CRS_DV asserted TPFI quiet to CRS_DV de-asserted Sym t1 t2 t3 t4 Min 4 2 - - Typ1 - - 3 13 Max - - - - Units ns ns BT BT Test Conditions - - - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Figure 31. 10BASE-T Transmit Timing REFCLK t1 TXD(1:0) t2 TPFO t4 t3 t5 TX_EN Table 28. 10BASE-T Transmit Timing Parameters Parameter TXD<1:0> setup to REFCLK rising edge TXD<1:0> hold from REFCLK rising edge TX_EN sampled to TPFO out (Tx latency) TX_EN setup to REFCLK rising edge TX_EN hold from REFCLK rising edge Sym t1 t2 t3 t4 t5 Min 4 2 - 4 2 Typ1 - - 15 - - Max - - - - - Units ns ns BT ns ns Test Conditions - - - - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 58 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Figure 32. Auto-Negotiation and Fast Link Pulse Timing Clock Pulse Data Pulse Clock Pulse TPFOP t1 t2 t3 Figure 33. Fast Link Pulse Timing t1 FLP Burst FLP Burst TPFOP t4 t5 Table 29. Auto-Negotiation and Fast Link Pulse Timing Parameters Parameter Clock/Data pulse width Clock pulse to Data pulse Clock pulse to Clock pulse FLP burst width FLP burst to FLP burst Clock/Data pulses per burst Sym t1 t2 t3 t4 t5 - Min - 55.5 111 - 8 17 Typ1 100 - - 2 - - Max - 69.5 139 - 24 33 Units ns Test Conditions - - - - - - s s ms ms ea 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Datasheet 59 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Figure 34. MDIO Write Timing (MDIO Sourced by MAC) MDC t1 t2 MDIO Figure 35. MDIO Read Timing (MDIO Sourced by PHY) MDC t3 MDIO Table 30. MDIO Timing Parameters Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced by STA MDC to MDIO output delay, sourced by PHY Sym t1 1 10 t2 1 10 t3 - 130 - ns MDC = 8 MHz - - - 300 ns ns MDC = 8 MHz MDC = 2.5 MHz - - - - ns ns MDC = 8 MHz MDC = 2.5 MHz Min 10 Typ1 - Max - Units ns Test Conditions MDC = 2.5 MHz 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 60 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Figure 36. Power-Up Timing v1 VCC MDIO,etc t1 Table 31. Power-Up Timing Parameters Parameter Voltage threshold Power Up delay Sym v1 t1 Min - - Typ1 2.9 - Max - 500 Units V ms Test Conditions - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Figure 37. RESET And Power-Down Recovery Timing RESET t1 t2 MDIO,etc Table 32. RESET and Power-Down Recovery Timing Parameters Parameter RESET pulse width RESET recovery delay Sym t1 t2 Min 10 - Typ1 - 1 Max - - Units ns ms Test Conditions - - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Datasheet 61 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII 5.0 Register Definitions The LXT97x1 register set includes multiple 16-bit registers. Table 33 presents a complete register listing and Table 34 provides a consolidated memory map of all registers. Table 35 through Table 49 define individual registers. * Base registers (0 through 8) are defined in accordance with the "Reconciliation Sublayer and Media Independent Interface" and "Physical Layer Link Signaling for 10/100 Mbps AutoNegotiation" sections of the IEEE 802.3 specification. * Additional registers (16 through 30) are defined in accordance with the IEEE 802.3 specification for adding unique chip functions. Table 33. Register Set Address 0 1 2 3 4 5 6 7 8 9 10 15 16 17 18 19 20 21-24 25 26 - 27 28 29 30 31 Control Register Status Register PHY Identification Register 1 PHY Identification Register 2 Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Base Page Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Transmit Register Auto-Negotiation Link Partner Received Next Page Register 1000BASE-T/100BASE-T2 Control Register 1000BASE-T/100BASE-T2 Status Register Extended Status Register Port Configuration Register Quick Status Register Interrupt Enable Register Interrupt Status Register LED Configuration Register Reserved Out of Band Signalling Register Reserved Transmit Control Register #1 Reserved Transmit Control Register #2 Reserved Refer to Table 51 on page 76 Refer to Table 50 on page 76 Refer to Table 49 on page 75 Register Name Bit Assignments Refer to Table 35 on page 65 Refer to Table 36 on page 65 Refer to Table 37 on page 66 Refer to Table 38 on page 67 Refer to Table 39 on page 67 Refer to Table 40 on page 68 Refer to Table 41 on page 69 Refer to Table 42 on page 69 Refer to Table 43 on page 70 Not Implemented Not Implemented Not Implemented Refer to Table 44 on page 70 Refer to Table 45 on page 71 Refer to Table 46 on page 72 Refer to Table 47 on page 73 Refer to Table 48 on page 74 62 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Table 34. Register Bit Map Bit Fields Reg Title B15 Control Register Control Status Register MF 100Base- 10Mbps 10Mbps 100Base- 100Base- Extended A/N Remote 100Base- 100Base- X Half Reserved Preamble T2 Full T2 Half Half Full X Full Status T4 Suppress Complete Fault Duplex Duplex Duplex Duplex Duplex Duplex PHY ID Registers PHY ID 1 PHY ID2 PHY ID No 15 14 13 12 11 10 9 8 7 6 MFR Model No Auto-Negotiation Advertisement Register A/N Advertise Pause Next Page Asymm Reserved Remote Reserved Pause Fault 10Base- 10Base100Base- 100Base- 100Base- T Full TX Full T TX T4 Duplex Duplex IEEE Selector Field 5 4 3 2 1 MFR Rev No 0 A/N Ability Link Status Extende d Jabber Detect Capabilit y Reset Loopbac k COL Test Speed Select A/N Enable Power Reserved Re-start A/N Down Duplex Mode Speed Select Reserved B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Add r 0 Status 1 2 3 4 Auto-Negotiation Link Partner Base Page Ability Register A/N Link Ability Ack Next Page Remote Reserved Asymm Pause Fault Pause 10Base- 10Base100Base100Base- TX Full 100Base- T Full T TX T4 Duplex Duplex Auto-Negotiation Expansion Register Link Parallel Partner Next Detect Page Fault Able Reserved Base Page Auto-Negotiation Next Page Transmit Register A/N Next Page Txmit Next Page Reserved Message Page Ack 2 Toggle Message / Unformatted Code Field Auto-Negotiation Link Partner Next Page Ability Register A/N Link Next Page Next Page Ack Message Page Ack 2 Toggle Message / Unformatted Code Field Port Configuration Register Link Port Config Reserved Disable Bypass Bypass Txmit Scramble 4B/5B r Disable (100TX) (100TX) Jabber (10T) SQE (10T) TP Loopbac Reserved k (10T) Quick Status Register FIFO Size Far End Alternat PRE_EN Reserve Reserve Fault Tx e Next d d Enable Page Fiber Select Next Page Able Link Page Receive Partner A/N Able d IEEE Selector Field 5 A/N Expansion 6 7 8 16 Datasheet 63 Bit Fields Reg Title B15 Quick Status Link Interrupt Enable Register Interrupt Enable Reserved Interrupt Status Register Reserved Auto-Neg Mask Speed Mask Duplex Mask Link Mask Reserve Reserve Interrupt Test d d Enable Interrupt Reserved 10/100 Mode Transmit Receiver Collision Status Status Status Duplex Auto-Neg Auto-Neg Reserved Polarity Complete Mode Pause B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 Error B2 B1 B0 Reserve Reserve Reserve d d d Add r 17 18 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Interrupt Status Reserved LED Configuration Register LED Config LED1 LED2 Reserved Auto-Neg Speed Done Change Duplex Link Reserve MD Reserve Reserve Change Change d Interrupt d d 19 LED3 LED Freq Pulse Invert Stretch Polarity 20 Programmable RMII Out of Band Signalling Register RMII OOB Signalling Reserved Transmit Control Register #1 Analog #1 Line Length Reserved Transmit Control Register #2 Analog #2 Reserved Driver Amp Reserved Bandwidth Control Slew Control Bit 1 Bit 0 Program RMII 25 28 30 64 Datasheet Table 34. Register Bit Map (Continued) Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Table 35. Control Register (Address 0) Bit 0.15 0.14 Reset Loopback Name 1 = PHY reset 0 = normal operation 1 = enable loopback mode 0 = disable loopback mode 0.6 0.13 Speed Selection 1 1 0 0 0.13 1 0 1 0 = Reserved = 1000 Mbps (not allowed) = 100 Mbps = 10 Mbps R/W Note 2 00 Description Type 1 R/W SC R/W Default 0 0 0.12 0.11 0.10 0.9 0.8 Auto-Negotiation Enable3 Power-Down Reserved Restart Auto-Negotiation Duplex Mode 1 = Enable Auto-Negotiation Process 0 = Disable Auto-Negotiation Process 1 = power-down 0 = normal operation Write as zero. Ignore on read. 1 = Restart Auto-Negotiation Process 0 = normal operation 1 = Full Duplex 0 = Half Duplex This bit is ignored by the LXT97x1. 1 = Enable COL signal test 0 = Disable COL signal test 0.6 0.13 1 0 1 0 = Reserved = 1000 Mbps (not allowed) = 100 Mbps = 10 Mbps 1 1 0 0 R/W R/W R/W R/W SC R/W Note 2 0 0 0 0 Note 2 0 0 0.7 Collision Test R/W 0.6 Speed Selection 1000 Mb/s R/W 00 0.5:0 Reserved Write as 0, ignore on Read R/W 00000 1. R/W = Read/Write RO = Read Only SC = Self Clearing 2. Default value of bits 0.12, 0.13 and 0.8 are determined by hardware pins. 3. Do not enable Auto-Negotiation if Fiber Mode is selected. Table 36. Status Register (Address 1) Bit 1.15 1.14 1.13 Name 100BASE-T4 100BASE-X Full Duplex 100BASE-X Half Duplex Description 1 = PHY able to perform 100BASE-T4 0 = PHY not able to perform 100BASE-T4 1 = PHY able to perform full-duplex 100BASE-X 0 = PHY not able to perform full-duplex 100BASE-X 1 = PHY able to perform half-duplex 100BASE-X 0 = PHY not able to perform half-duplex 100BASE-X Type 1 RO RO RO Defaul t 0 1 1 1. RO = Read Only LL = Latching Low LH = Latching High 2. Bit 1.4 is not valid if Auto-Negotiation is selected while operating in Fiber mode. Datasheet 65 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 36. Status Register (Address 1) (Continued) Bit 1.12 1.11 1.10 1.9 1.8 1.7 1.6 Name 10 Mbps Full Duplex 10 Mbps Half Duplex 100BASE-T2 Full Duplex 100BASE-T2 Half Duplex Extended Status Reserved MF Preamble Suppression Auto-Negotiation complete Remote Fault2 Auto-Negotiation Ability Link Status Jabber Detect Extended Capability Description 1 = PHY able to operate at 10 Mbps in full-duplex mode 0 = PHY not able to operate at 10 Mbps full-duplex mode 1 = PHY able to operate at 10 Mbps in half-duplex mode 0 = PHY not able to operate at 10 Mbps in half-duplex 1 = PHY able to perform full-duplex 100BASE-T2 0 = PHY not able to perform full-duplex 100BASE-T2 1 = PHY able to perform half duplex 100BASE-T2 0 = PHY not able to perform half-duplex 100BASE-T2 1 = Extended status information in register 15 0 = No extended status information in register 15 1 = ignore when read 1 = PHY will accept management frames with preamble suppressed 0 = PHY will not accept management frames with preamble suppressed 1 = Auto-negotiation complete 0 = Auto-negotiation not complete 1 = Remote fault condition detected 0 = No remote fault condition detected 1 = PHY is able to perform Auto-Negotiation 0 = PHY is not able to perform Auto-Negotiation 1 = Link is up 0 = Link is down 1 = Jabber condition detected 0 = Jabber condition not detected 1 = Extended register capabilities 0 = Extended register capabilities Type 1 RO RO RO RO RO RO RO Defaul t 1 1 0 0 0 0 0 1.5 1.4 1.3 1.2 1.1 1.0 RO RO/LH RO RO/LL RO/LH RO 0 0 1 0 0 1 1. RO = Read Only LL = Latching Low LH = Latching High 2. Bit 1.4 is not valid if Auto-Negotiation is selected while operating in Fiber mode. Table 37. PHY Identification Register 1 (Address 2) Bit 2.15:0 Name PHY ID Number Description The PHY identifier composed of bits 3 through 18 of the OUI. Type 1 RO Default 0013 hex 1. RO = Read Only 66 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Table 38. PHY Identification Register 2 (Address 3) Bit 3.15:10 3.9:4 3.3:0 Name PHY ID number Manufacturer's model number Manufacturer's revision number Description The PHY identifier composed of bits 19 through 24 of the OUI. 6 bits containing manufacturer's part number. 4 bits containing manufacturer's revision number. Type 1 RO RO RO Default 011110 000111 (LXT9761) 001010 (LXT9781) XXXX 1. RO = Read Only Figure 38. PHY Identifier Bit Mapping a b c r s x Organizationally Unique Identifier 1 2 3 0 0 1 3 18 19 24 I/G 15 0 15 10 9 4 3 0 PHY ID Register #1 (Address 2) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 PHY ID Register #2 (Address 3) 1 1 0 X X X X X X X X X X 0 0 0 2 B 7 5 0 3 0 00 20 7B The One The Level Intel OUI is 00207B hex. Manufacturer's Model Number Revision Number Table 39. Auto-Negotiation Advertisement Register (Address 4) Bit 4.15 4.14 4.13 4.12 4.11 4.10 Name Next Page Reserved Remote Fault Reserved Asymmetric Pause Pause Description 1 = Port has ability to send multiple pages. 0 = Port has no ability to send multiple pages. Ignore. 1 = Remote fault. 0 = No remote fault. Ignore. Pause operation defined in Clause 40 and 27 1 = Pause operation enabled for full-duplex links. 0 = Pause operation disabled. Type 1 R/W RO R/W R/W R/W R/W Default 0 0 0 0 0 Note 2 1. R/W = Read/Write RO = Read Only 2. The default setting of bit 4.10 (PAUSE) is determined by pin 79. 3. Default settings for bits 4.5:8 are determined by LED?CFG pins as described in Table 9 on page 29. Datasheet 67 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 39. Auto-Negotiation Advertisement Register (Address 4) (Continued) Bit Name Description 1 = 100BASE-T4 capability is available. 0 = 100BASE-T4 capability is not available. 4.9 100BASE-T4 (The LXT97x1 does not support 100BASE-T4 but allows this bit to be set to advertise in the Auto-Negotiation sequence for 100BASE-T4 operation. An external 100BASE-T4 transceiver could be switched in if this capability is desired.) 1 = Port is 100BASE-TX full duplex capable. 0 = Port is not 100BASE-TX full duplex capable. 1 = Port is 100BASE-TX capable. 0 = Port is not 100BASE-TX capable. 1 = Port is 10BASE-T full duplex capable. 0 = Port is not 10BASE-T full duplex capable. 1 = Port is 10BASE-T capable. 0 = Port is not 10BASE-T capable. <00001> = IEEE 802.3. <00010> = IEEE 802.9 ISLAN-16T. <00000> = Reserved for future Auto-Negotiation development. <11111> = Reserved for future Auto-Negotiation development. Unspecified or reserved combinations should not be transmitted. R/W 0 Type 1 Default 4.8 4.7 4.6 4.5 100BASE-TX full duplex 100BASE-TX 10BASE-T full duplex 10BASE-T R/W R/W R/W R/W Note 2 Note 2 Note 2 Note 2 4.4:0 Selector Field, S<4:0> R/W 00001 1. R/W = Read/Write RO = Read Only 2. The default setting of bit 4.10 (PAUSE) is determined by pin 79. 3. Default settings for bits 4.5:8 are determined by LED?CFG pins as described in Table 9 on page 29. Table 40. Auto-Negotiation Link Partner Base Page Ability Register (Address 5) Bit 5.15 Name Next Page Description 1 = Link Partner has ability to send multiple pages. 0 = Link Partner has no ability to send multiple pages. 1 = Link Partner has received Link Code Word from LXT97x1. 0 = Link Partner has not received Link Code Word from the LXT97x1. 1 = Remote fault. 0 = No remote fault. Ignore. Pause operation defined in Clause 40 and 27. 1 = Link Partner is Pause capable. 0 = Link Partner is not Pause capable. 1 = Link Partner is Pause capable. 0 = Link Partner is not Pause capable. 1 = Link Partner is 100BASE-T4 capable. 0 = Link Partner is not 100BASE-T4 capable. 1 = Link Partner is 100BASE-TX full duplex capable. 0 = Link Partner is not 100BASE-TX full duplex capable. 1 = Link Partner is 100BASE-TX capable. 0 = Link Partner is not 100BASE-TX capable. RO 0 Type 1 RO Default 0 5.14 Acknowledge RO 0 5.13 5.12 5.11 Remote Fault Reserved Asymmetric Pause Pause 100BASE-T4 100BASE-TX full duplex 100BASE-TX RO RO 0 0 5.10 5.9 5.8 5.7 RO RO RO RO 0 0 0 0 1. RO = Read Only 68 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Table 40. Auto-Negotiation Link Partner Base Page Ability Register (Address 5) (Continued) Bit 5.6 5.5 Name 10BASE-T full duplex 10BASE-T Description 1 = Link Partner is 10BASE-T full duplex capable. 0 = Link Partner is not 10BASE-T full duplex capable. 1 = Link Partner is 10BASE-T capable. 0 = Link Partner is not 10BASE-T capable. <00001> = IEEE 802.3. <00010> = IEEE 802.9 ISLAN-16T. <00000> = Reserved for future Auto-Negotiation development. <11111> = Reserved for future Auto-Negotiation development. Unspecified or reserved combinations shall not be transmitted. Type 1 RO RO Default 0 0 5.4:0 Selector Field S<4:0> RO 00000 1. RO = Read Only Table 41. Auto-Negotiation Expansion (Address 6) Bit 6.15:6 Name Reserved Ignore on read. This bit indicates the status of the Auto_Negotiation variable, base page. It flags synchronization with the Auto_Negotiation state diagram allowing detection of interrupted links. This bit is only used if bit 16.1 (Alternate NP feature) is set. 1 = base_page = true 0 = base_page = false 6.4 6.3 6.2 Parallel Detection Fault Link Partner Next Page Able Next Page Able 1 = Parallel detection fault has occurred. 0 = Parallel detection fault has not occurred. 1 = Link partner is next page able. 0 = Link partner is not next page able. 1 = Local device is next page able. 0 = Local device is not next page able. 1 = 3 identical and consecutive link code words have been received from link partner. 0 = 3 identical and consecutive link code words have not been received from link partner. 1 = Link partner is auto-negotiation able. 0 = Link partner is not auto-negotiation able. RO/ LH RO RO 0 0 1 Description Type 1 RO Default 0 6.5 Base Page RO 0 6.1 Page Received RO LH 0 6.0 Link Partner A/N Able RO 0 1. RO = Read Only LH = Latching High Table 42. Auto-Negotiation Next Page Transmit Register (Address 7) Bit 7.15 7.14 7.13 Name Next Page (NP) Reserved Message Page (MP) Description 1 = Additional next pages follow. 0 = Last page. Write as 0, ignore on read. 1 = Message page. 0 = Unformatted page. Type 1 R/W RO R/W Default 0 0 1 1. R/W = Read Write RO = Read Only Datasheet 69 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 42. Auto-Negotiation Next Page Transmit Register (Address 7) Bit 7.12 Name Acknowledge 2 (ACK2) Toggle (T) Message/Unformatted Code Field Description 1 = Will comply with message. 0 = Can not comply with message. 1 = Previous value of the transmitted Link Code Word equalled logic zero. 0 = Previous value of the transmitted Link Code Word equalled logic one. Type 1 R/W Default 0 7.11 R/W 0 7.10:0 R/W 00000000001 1. R/W = Read Write RO = Read Only Table 43. Auto-Negotiation Link Partner Next Page Receive Register (Address 8) Bit 8.15 8.14 8.13 8.12 8.11 8.10:0 Name Next Page (NP) Acknowledge (ACK) Message Page (MP) Acknowledge 2 (ACK2) Toggle (T) Message/Unformatted Code Field Description 1 = Link Partner has additional next pages to send. 0 = Link Partner has no additional next pages to send. 1 = Link Partner has received Link Code Word from LXT97x1. 0 = Link Partner has not received Link Code Word from LXT97x1. 1 = Page sent by the Link Partner is a Message Page. 0 = Page sent by the Link Partner is an Unformatted Page. 1 = Link Partner Will comply with the message. 0 = Link Partner can not comply with the message. 1 = Previous value of the transmitted Link Code Word equalled logic zero. 0 = Previous value of the transmitted Link Code Word equalled logic one. Type 1 RO RO RO RO RO RO Default 0 0 0 0 0 0 1. RO = Read Only Table 44. Port Configuration Register (Address 16, Hex 10) Bit 16.15 16.14 16.13 16.12 16.11 16.10 Name Reserved Force Link Pass Transmit Disable Bypass Scramble (100BASE-TX) Reserved Jabber (10BASE-T) Write as zero. Ignore on read. 1 = Force Link Pass. Sets appropriate registers and LEDs to Pass. 0 = Normal operation. 1 = Disable Twisted Pair transmitter. 0 = Normal Operation. 1 = Bypass Scrambler and Descrambler. 0 = Normal Operation. Write as zero. Ignore on read. 1 = Disable Jabber. 0 = Normal operation. Description Type 1 R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 1. R/W = Read /Write 2. The default value of bit 16.0 is determined by the SD/TPn pin for the respective port. If SD/TPn is tied Low, the default value of bit 16.0 = 0. If SD/TPn is not tied Low, the default value of bit 16.0 = 1. 70 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Table 44. Port Configuration Register (Address 16, Hex 10) Bit Name SQE (10BASE-T) TP Loopback (10BASE-T) CRS Select (10BASE-T) Description This bit is ignored by the LXT97x1. 1 = Enable Heart Beat. 0 = Disable Heart Beat. 1 = Disable TP loopback during half duplex operation. 0 = Normal Operation. 1 = CRS de-assert extends to RXDV de-assert. 0 = Normal operation. 0 = FIFO allows packets up to 2 KBytes. 1 = FIFO allows packets up to 10 KBytes. Packet sizes assume a 450 ppm difference between the reference clock and the recovered clock. Preamble Enable. 0 = Set RX_DV high coincident with SFD. 1 = Set RX_DV high and RXD=preamble when CRS is asserted. Write as zero. Ignore on read. Write as zero. Ignore on read. 1 = Enable Far End Fault code transmission. 0 = Disable Far End Fault code transmission. 1 = Enable alternate auto-negotiate next page feature. 0 = Disable alternate auto-negotiate next page feature. 1 = Select fiber mode for this port. 0 = Select TP mode for this port. R/W 0 Type 1 Default 16.9 16.8 16.7 R/W R/W 1 1 16.6 FIFO Size R/W 0 16.5 16.4 16.3 16.2 16.1 16.0 PRE_EN (10BASE-T) Reserved Reserved Far End Fault Transmit Enable Alternate NP feature Fiber Select R/W R/W R/W R/W R/W R/W 0 0 0 1 0 Note 2 1. R/W = Read /Write 2. The default value of bit 16.0 is determined by the SD/TPn pin for the respective port. If SD/TPn is tied Low, the default value of bit 16.0 = 0. If SD/TPn is not tied Low, the default value of bit 16.0 = 1. Table 45. Quick Status Register (Address 17, Hex 11) Bit 17.15 17.14 17.13 17.12 17.11 17.10 17.9 17.8 Name Reserved 10/100 Mode Transmit Status Receive Status Collision Status Link Duplex Mode Auto-Negotiation Always 0. 1 = LXT97x1 is operating in 100BASE-TX mode. 0 = LXT97x1 is not operating 100BASE-TX mode. 1 = LXT97x1 is transmitting a packet. 0 = LXT97x1 is not transmitting a packet. 1 = LXT97x1 is receiving a packet. 0 = LXT97x1 is not receiving a packet. 1 = Collision is occurring. 0 = No collision. 1 = Link is up. 0 = Link is down. 1 = Full duplex. 0 = Half duplex. 1 = LXT97x1 is in Auto-Negotiation Mode. 0 = LXT97x1 is in manual mode. Description Type 1 RO RO RO RO RO RO RO RO Default 0 0 0 0 0 0 0 0 1. RO = Read Only Datasheet 71 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 45. Quick Status Register (Address 17, Hex 11) Bit Name Description 1 = Auto-negotiation process completed. 0 = Auto-negotiation process not completed. This bit is only valid when auto-negotiate is enabled, and is equivalent to bit 1.5. Reserved. 1= Polarity is reversed. 0= Polarity is not reversed. 1 = The LXT97x1 is Pause capable. 0 = The LT97x1 is Not Pause capable. 1 = Error Occurred (Remote Fault, X,Y,Z). 0 = No error occurred. Ignore. Type 1 Default 17.7 Auto-Negotiation Complete Reserved Polarity Pause Error Reserved RO 0 17.6 17.5 17.4 17:3 17:2:0 RO RO RO RO RO 0 0 0 0 0 1. RO = Read Only Table 46. Interrupt Enable Register (Address 18, Hex 12) Bit 18.15:8 18.7 Name Reserved ANMSK Write as 0; ignore on read. Mask for Auto-Negotiate Complete 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Mask for Speed Interrupt 18.6 SPEEDMSK 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Mask for Duplex Interrupt 18.5 DUPLEXMSK 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Mask for Link Status Interrupt 18.4 18.3 18.2 18.1 18.0 LINKMSK Reserved Reserved INTEN TINT 1 = Enable event to cause interrupt. 0 = Do not allow event to cause interrupt. Write as 0, ignore on read. Write as 0, ignore on read. 1 = Enable interrupts on this port. 0 = Disable interrupts on this port. 1 = Force interrupt on MDINT. 0 = Normal operation. R/W R/W R/W R/W R/W 0 0 0 0 0 R/W 0 R/W 0 R/W 0 Description Type 1 R/W Default N/A 1. R/W = Read /Write 72 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Table 47. Interrupt Status Register (Address 19, Hex 13) Bit 19.15:8 19.7 Name Reserved ANDONE Ignore Auto-Negotiation Status 1= Auto-Negotiation has completed. 0= Auto-Negotiation has not completed. Speed Change Status 19.6 SPEEDCHG 1 = A Speed Change has occurred since last reading this register. 0 = A Speed Change has not occurred since last reading this register. Duplex Change Status 19.5 DUPLEXCHG 1 = A Duplex Change has occurred since last reading this register. 0 = A Duplex Change has not occurred since last reading this register. Link Status Change Status 19.4 19.3 19.2 19.1:0 LINKCHG Reserved MDINT Reserved 1 = A Link Change has occurred since last reading this register. 0 = A Link Change has not occurred since last reading this register. Ignore. 1 = RMII interrupt pending. 0 = No RMII interrupt pending. Ignore. RO/SC RO RO/SC RO 0 0 0 0 RO/SC 0 RO/SC 0 RO/SC N/A Description Type 1 RO Default N/A 1. R/W = Read/Write RO = Read Only SC = Self Clearing Datasheet 73 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 48. LED Configuration Register (Address 20, Hex 14) Bit Name Description 0000 = Display Speed Status (Continuous, Default). 0001 = Display Transmit Status (Stretched). 0010 = Display Receive Status (Stretched). 0011 = Display Collision Status (Stretched). 0100 = Display Link Status (Continuous). 0101 = Display Duplex Status (Continuous)5. 0110 =Reserved. 0111 = Display Receive or Transmit Activity (Stretched). 1000 = Test mode- turn LED on (Continuous). 1001 = Test mode- turn LED off (Continuous). 1010 = Test mode- blink LED fast (Continuous). 1011 = Test mode- blink LED slow (Continuous). 1100 = Display Link and Receive Status combined 2 (Stretched)3 . 1101 = Display Link and Activity Status combined 2 (Stretched)3. 1110 = Display Duplex & Collision Status combined 4 (Stretched)3,5. 1111 = Reserved. 0000 = Display Speed Status. 0001 = Display Transmit Status. 0010 = Display Receive Status. 0011 = Display Collision Status. 0100 = Display Link Status (Default). 0101 = Display Duplex Status5. 0110 = Reserved. 0111 = Display Receive or Transmit Activity. 1000 = Test mode- turn LED on. 1001 = Test mode- turn LED off. 1010 = Test mode- blink LED fast. 1011 = Test mode- blink LED slow. 1100 = Display Link and Receive Status combined 2 (Stretched)3. 1101 = Display Link and Activity Status combined 2 (Stretched)3. 1110 = Display Duplex & Collision Status combined 4 (Stretched)3,5. 1111 = Reserved. 0000 = Display Speed Status. 0001 = Display Transmit Status. 0010 = Display Receive Status (Default). 0011 = Display Collision Status. 0100 = Display Link Status. 0101 = Display Duplex Status5. 0110 = Reserved. 0111 = Display Receive or Transmit Activity. 1000 = Test mode- turn LED on. 1001 = Test mode- turn LED off. 1010 = Test mode- blink LED fast. 1011 = Test mode- blink LED slow. 1100 = Display Link and Receive Status combined 2 (Stretched)3. 1101 = Display Link and Activity Status combined 2 (Stretched)3. 1110 = Display Duplex & Collision Status combined 4 (Stretched)3,5. 1111 = Reserved. Type 1 Default LED1 20.15:12 Programming bits R/W 0000 LED2 20.11:8 Programming bits R/W 0100 LED3 20.7:4 Programming bits R/W 0010 1. R/W = Read /Write RO = Read Only LH = Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (Receive or Activity) causes the LED to change state (blink). 3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched regardless of the value of 20.1. 4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Duplex LED maybe active for a brief time after loss of link. 74 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 Table 48. LED Configuration Register (Address 20, Hex 14) (Continued) Bit Name Description 00 = Stretch LED events to 30 ms. 01 = Stretch LED events to 60 ms. 10 = Stretch LED events to 100 ms. 11 = Reserved. 1 = Enable pulse stretching of all LEDs. 0 = Disable pulse stretching of all LEDs 2. 1 = Use active High polarity for serial LEDs. 0 = Use active Low polarity for serial LEDs. Type 1 Default 20.3:2 LEDFREQ R/W 00 20.1 20.0 PULSESTRETCH INVPOL R/W R/W 1 0 1. R/W = Read /Write RO = Read Only LH = Latching High 2. Link status is the primary LED driver. The LED is asserted (solid ON) when the link is up. The secondary LED driver (Receive or Activity) causes the LED to change state (blink). 3. Combined event LED settings are not affected by Pulse Stretch bit 20.1. These display settings are stretched regardless of the value of 20.1. 4. Duplex status is the primary LED driver. The LED is asserted (solid ON) when the link is full duplex. Collision status is the secondary LED driver. The LED changes state (blinks) when a collision occurs. 5. Duplex LED maybe active for a brief time after loss of link. Table 49. Out of Band Signaling Register (Address 25) Bit 25:15:7 Name Reserved Reserved. These 3 bits select which status information is available on the RXD(1) bit of the RMII bus. 000 = Link 001 = Speed 010 = Duplex 25:6:4 BIT1 011 = Auto-negotiation complete 100 = Polarity reversed 101 = Jabber detected 110 = Interrupt pending 111 = Reserved These 3 bits select which status information is available on the RXD(0) bit of the RMII bus. 000 = Link 001 = Speed 010 = Duplex 25.3:1 BIT0 011 = Auto-negotiation complete 100 = Polarity reversed 101 = Jabber detected 110 = Interrupt pending 111 = Reserved 25.0 PROGRMII 1 = Enable programmable RMII Out of Band signalling. When enabled, bits 6:1 specify which status bits are available on the RMII RXD data bus. 0 = Disable Out of Band signalling. 1. R/W = Read/Write RO = Read Only R/W 0 R/W 000 R/W 000 Description Type 1 R/W Default 0 Datasheet 75 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Table 50. Transmit Control Register #1 (Address 28) Bit 28.15:4 Name Reserved Bandwidth Control Ignore. 00 = Nominal Differential Amp Bandwidth 01 = Slower 10 = Fastest 11 = Faster 00 = 2.5ns 01 = 3.1ns 10 = 3.7ns 11 = 4.3ns Description Type2 R/W Default N/A 28.3:2 R/W 00 28.1:0 Risetime Control R/W Note 3 1. Transmit Control functions are approximations. They are not guaranteed and not subject to production testing. 2. RO = Read Only. R/W = Read/Write. 3. The default setting of bits 28.1:0 (Risetime) are determined by pins 91 and 94. Table 51. Transmit Control Register #2 (Address 30) Bit 30.15:14 30.13 30.12:0 Reserved Increase Driver Amplitude Reserved 1 = Increase Driver Amplitude 5% in all modes. 0 = Normal operation. Name Description Type R/W R/W R/W Default N/A 0 N/A 1. RO = Read Only. 76 Datasheet Fast Ethernet 10/100 Multi-Port Transceiver with RMII -- LXT9761/9781 6.0 Package Specifications Figure 39. LXT97x1 PQFP Specification 208-Pin Plastic Quad Flat Package * Part Number LXT9761HC (6-port model) * Part Number LXT9781HC (8-port model) * Commercial Temperature Range (0C to 70C) D D1 Millimeters Dim Min A A1 e Max 4.10 3.60 0.27 30.90 28.30 30.90 28.30 .50 BASIC 0.25 3.20 0.17 30.30 27.70 30.30 27.70 E1 A2 E e b /2 D D1 E E1 2 L1 A A2 A1 L b 3 e L L1 q 0 5 5 0.50 0.75 1.30 REF 7 16 16 2 3 Datasheet 77 LXT9761/9781 -- Fast Ethernet 10/100 Multi-Port Transceiver with RMII Figure 40. LXT9781 PBGA Specification 272-Lead Plastic Ball Grid Array * Part Number LXT9781BC (8-port model) * Commercial Temperature Range (0C to 70C) 24.13 1.435 REF 1.27 27.00 0.20 24.00 0.20 8.00 0.10 PIN #A1 CORNER 0.75 0.15 A B C D E F G 1.27 PIN #A1 ID 8.00 0.10 H J K L 27.00 0.20 24.00 0.20 24.13 M N P R T U V W Y O1.00 (3 plcs) TOP VIEW 20 19 18 17 16 15 14 13 12 11 10 9 8 76 54 3 21 1.435 REF BOTTOM VIEW 0.92 0.05 2.13 0.19 NOTE: 1. ALL DIMENSIONS IN MILLIMETERS 2. ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y 14.5M-1994 3. TOLERANCE = 0.05 UNLESS SPECIFIED OTHERWISE SEATING PLANE 0.61 0.04 0.60 0.10 SIDE VIEW 78 Datasheet |
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